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cml microcircuits communication semiconductor s CMX148 pmr audio and data processor ? 2010 cml microsystems plc d/148/6 november 2010 audio processing, dtmf and ffsk/msk data modem with auxiliary functions for use in analogue pmr systems features ? concurrent audio/signalling/data operations ? dual auxiliary adc, 4 multiplexed inputs ? complete audio-band processing: o selectable audio processing order o pre and de-emphasis o selectable 2.55/3.0 khz filtering o selectable audio hpf cut-off o compandor o limiter ? 4 x auxiliary dacs ? dual programmable system clock outputs ? tx outputs for single, two-point or i/q modulation ? microphone and discriminator analogue inputs ? programmable voice scrambler ? digital gain adjustment ? msk/ffsk data modem with packet or free- format modes with fec, crc, interleaving and scrambling ? default 3.6864mhz xtal/clock ? c-bus serial interface to host controller ? dtmf and audio tone encoder/decoder ? flexible powersave modes ? routing to support host controller signalling ? low-power 3.3v operation ? sub-audio signalling filters for ctcss and dcs ? small vqfn and lqfp packages modulator rf discriminator host c auxiliary multiplexed adc inputs CMX148 pmr voice and data processor rx enable tx enable irq host generated signalling filtered signal for host decoding c-bus system clock 1 reference clock 3.3v supply system clock 2 auxiliary dacs mic input audio out 1. brief description the CMX148 is a half-duplex, audio, signalling and data pr ocessing ic for use in pmr systems that utilise the host c to perform signalling, including ctc ss/dcs encoding/decoding. the device is intended for use in general leisure and professional pmr terminals. comprehensive audio processing facilities include comple te audio processing, filtering, companding, pre- or de-emphasis and frequency inversion scrambling. the CMX148 features an ffsk/msk data modem for packetised or free-format data operations. signal routing and filtering is included to assist host c based signal encoding/decoding applications. a dtmf encoder/decoder, a full complement of aux iliary adcs and dacs and dual synthesised clock outputs are included in this low power pmr processor. the device also has flexible powersaving modes and is available in 48-pin vqfn and lqfp packages.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 2 d/148/6 contents section page 1. brief descr iption.............................................................................................................. ....... 1 1.1. history........................................................................................................................ .. 5 2. block di agram .................................................................................................................. ...... 6 3. signal list.................................................................................................................... ............ 7 4. external co mponents ............................................................................................................ 9 5. pcb layout guidelines and power supply decoupling................................................... 11 6. general d escripti on ............................................................................................................ . 12 7. detailed d escripti ons.......................................................................................................... . 13 7.1. device identif ication code......................................................................................... 13 7.2. xtal fr equency .......................................................................................................... 13 7.3. host inte rface ............................................................................................................ 13 7.4. device c ontrol ........................................................................................................... 15 7.4.1. signal r outing..................................................................................................... 15 7.4.2. mode cont rol ...................................................................................................... 16 7.5. audio f uncti ons......................................................................................................... 17 7.5.1. audio rece ive mode........................................................................................... 17 7.5.2. audio trans mit mode.......................................................................................... 20 7.6. external sub-a udio signa lling................................................................................... 26 7.7. inband signa lling ....................................................................................................... 26 7.7.1. receiving dt mf tones ...................................................................................... 27 7.7.2. transmitting dt mf tones .................................................................................. 27 7.7.3. transmitting a udio t ones ................................................................................... 27 7.8. msk/ffsk da ta modem ........................................................................................... 27 7.8.1. receiving msk/ ffsk signals ............................................................................ 28 7.8.2. transmitting msk/ ffsk signals ........................................................................ 28 7.9. msk/ffsk data packetising .................................................................................... 29 7.9.1. tx hang bit ......................................................................................................... 29 7.9.2. frame fo rmat ..................................................................................................... 29 7.9.3. frame head ........................................................................................................ 29 7.9.4. data blo ck coding .............................................................................................. 30 7.9.5. crc and fec encoding information.................................................................. 31 7.9.6. data inte rleaving................................................................................................. 31 7.9.7. data scrambling/ privacy coding ........................................................................ 31 7.9.8. data buffe r timing .............................................................................................. 32 7.10. auxiliary adc operation ........................................................................................... 32 7.11. auxiliary dac/ramd ac oper ation........................................................................... 33 7.12. digital system clock g enerat or ................................................................................ 34 7.12.1. main clock operation ......................................................................................... 35 7.12.2. system clock operation ..................................................................................... 35 7.13. gpio.......................................................................................................................... 35 7.14. signal level op timisation .......................................................................................... 35 7.14.1. transmit path levels .......................................................................................... 35
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 3 d/148/6 7.14.2. receive path levels ........................................................................................... 36 8. configurati on guide............................................................................................................ . 37 8.1. c-bus regist er details ............................................................................................. 37 8.1.1. reset oper ations ................................................................................................ 38 8.1.2. general reset - $01 wr ite ................................................................................... 38 8.1.3. interrupt o peration.............................................................................................. 38 8.1.4. general notes ..................................................................................................... 38 8.1.5. auxadc and tx mod m ode - $a7 write ............................................................ 39 8.1.6. auxdac control/da ta - $a8 write....................................................................... 40 8.1.7. auxadc1 data - $a9 read.................................................................................. 41 8.1.8. auxadc2 data - $aa read ................................................................................. 41 8.1.9. sysclk1 and sysclk2 pll data - $ab, $a d write........................................ 41 8.1.10. sysclk1 and sysclk2 ref - $ac and $ae write ......................................... 42 8.1.11. analogue output gain - $b0 write ...................................................................... 43 8.1.12. input gain and output signal routing - $b1 write.............................................. 44 8.1.13. reserved - $b 2 write .......................................................................................... 44 8.1.14. reserved - $b 3 write .......................................................................................... 44 8.1.15. reserved - $b4 read........................................................................................... 44 8.1.16. auxadc threshold da ta - $b5 write .................................................................. 45 8.1.17. modem address - $b6 wr ite ............................................................................... 45 8.1.18. reserved - $bb read .......................................................................................... 45 8.1.19. powerdown contro l - $c0 write .......................................................................... 45 8.1.20. mode control ? $c1 wr ite ................................................................................... 46 8.1.21. audio control ? $c2 wr ite ................................................................................... 47 8.1.22. tx inband tones - $c3 wr ite .............................................................................. 47 8.1.23. status ? $c6 r ead ............................................................................................... 48 8.1.24. modem control - $c7 wr ite ................................................................................. 49 8.1.25. programming register ? $c8 write..................................................................... 50 8.1.26. rx data 1 and 2 - $c5 and $c 9 read ................................................................. 50 8.1.27. tx data 1 and 2 - $ca and $cb write ................................................................ 51 8.1.28. tone status - $cc read ...................................................................................... 51 8.1.29. audio tone - $ cd: write...................................................................................... 52 8.1.30. interrupt mask - $ce wr ite .................................................................................. 54 8.1.31. reserved - $c f write .......................................................................................... 54 8.2. programming register oper ation.............................................................................. 55 8.2.1. program block 0 ? m odem confi guration........................................................... 56 8.2.2. program block 1 ? inband tone setup............................................................... 57 8.2.3. program block 2 ? ct css and dcs setup ....................................................... 58 8.2.4. program block 3 ? auxdac, ramdac and clo ck cont rol ................................ 59 8.2.5. program block 4 ? gain and offset setup.......................................................... 60 8.2.6. initialisation of t he program blocks..................................................................... 63 9. performance sp ecification .................................................................................................. 64 9.1. electrical pe rformance .............................................................................................. 64 9.1.1. absolute maxi mum ra tings ................................................................................ 64 9.1.2. operating limits .................................................................................................. 64 9.1.3. operating char acteristics ................................................................................... 65 9.1.4. parametric pe rform ance ..................................................................................... 70 9.2. c-bus ti ming............................................................................................................ 73
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 4 d/148/6 9.3. packaging.................................................................................................................. 74 table page table 1 xtal/clock frequency settings for progr am blo ck 3 ........................................................ 13 table 2 dtmf tone pa irs....................................................................................................... ...... 27 table 3 data frequencie s for each baud rate ............................................................................ 29 table 4 data block formats .................................................................................................... ..... 31 table 5 maximum da ta transfe r latenc y..................................................................................... 32 table 6 rese t operat ions ...................................................................................................... ....... 38 table 7 audio tone regi ster - att enuation steps ........................................................................ 53 table 8 program bl ock selection................................................................................................ ... 55 table 9 ramd ac va lues ......................................................................................................... .... 59 figure page figure 1 bl oc k di agram .................................................................................................................. 6 figure 2 recommended external co mponents ............................................................................. 9 figure 3 power supply and dec oupling ....................................................................................... 11 figure 4 c-bu s transac tions ................................................................................................... .... 14 figure 5 signal routing ....................................................................................................... ......... 16 figure 6 adjustabl e hpf re sponse ............................................................................................. 18 figure 7 rx 25khz channel a udio filter fr equency res ponse................................................... 18 figure 8 rx 12.5khz channel a udio filter fr equency res ponse................................................. 19 figure 9 de-em phasis 12. 5khz ................................................................................................... .. 19 figure 10 tx channel audio filter response and temp late (etsi) ............................................ 21 figure 11 tx channel audio filter response and temp late (tia) .............................................. 21 figure 12 audio frequency pre- emphas is ................................................................................... 22 figure 13 audio fr equency pre- emphas is .................................................................................... 23 figure 14 expandor tr ansient re sponse ..................................................................................... 25 figure 15 compressor transient respons e................................................................................. 25 figure 16 external signa lling filter respons e............................................................................... 26 figure 17 modulating waveforms for 1200 and 2400 baud m sk/ffsk signals ......................... 29 figure 18 digital clo ck generati on schem es............................................................................... 34 figure 19 level adjustments ................................................................................................... ..... 36 figure 20 limi ter va lues ...................................................................................................... ......... 61 figure 21 default tx audio filter line-up ..................................................................................... 62 figure 22 default rx audio filter line-up..................................................................................... 62 figure 23 preferred tx audio filter line-up ................................................................................. 63 figure 24 preferred rx audio filter line-up ................................................................................. 63 figure 25 c- bus ti ming........................................................................................................ ....... 73 figure 26 mechanical outli ne of 48-pin vqfn (q3)..................................................................... 74 figure 27 mechanical outli ne of 48-pin lqfp (l4) ........................................................................ 1 it is always recommended that you check for the late st product datasheet version from the cml website: [ www.cmlmicro.com ].
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 5 d/148/6 1.1. history version changes date ? 6 ? removal of spurious notes 32 and 33, section 9.1.3 ? enhanced description of c-bus latency time, just before fig 4. ? correction to audio tone ($cd) register, code 1100 b , section 8.1.29. ? correction to program block 4, register s p4.7, p4.10, p4.11, section 8.2.5. 25 nov 10 5 ? first documentation release 09 jul 09 2-4 ? internal documentation updates 11 mar 09 1 ? initial document created ? bas ed on 7031/7041fi-1.3 documentation 02 jul 08
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 6 d/148/6 2. block diagram auxiliary systems control systems core operations and routing rx audio processing sub-audio signalling support disc sig mic bpf voice filter de-emphasis de- scrambler expander voice filter compressor pre- emphasis scrambler channel filter tx audio processing data modem ffsk/msk demodulator free format flexible packet in-band signalling dtmf decoder programmable tone encoder mod1 mod2/ sigout audio modulation mode (sections can be de-selected and processing order is programmable) (sections can be de-selected and processing order is programmable) filter ctcss/dcs/bypass v bias (free format and flexible packet operation are selectable ) (programmable tone and dtmf operations are selectable) ffsk/msk modulator free format flexible packet dtmf encoder hpf v bias v bias dacs dac 1 dac 2 dac 3 dac 4 ramp profile ram dac outputs adc inputs adc 1 adc 2 adcs system clocks synthesised clocks level thresholds averaging configured io digital io sysclk1 txena rxena sysclk2 mux level thresholds averaging irqn rdata cdata csn sclk c-bus interface crystal oscillator main pll and dividers xtaln xtal/clk registers dvdd dvss vdec avdd avss vbias power control regulator bias soft limiter channel filter figure 1 block diagram
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 7 d/148/6 3. signal list 48-pin q3/l4 signal name type CMX148 description 1 dvss pwr digital ground 2 vdec pwr internally generated 2.5v s upply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections allowed., exc ept for the optional connection to rfv dd . 3 xtal/clk ip input to the oscillator inverter fr om the xtal circuit or external clock source 4 xtaln op the output of the on-ch ip xtal oscillator inverter 5 dvdd pwr the 3.3v positive supply rail for the digital on-chip circuits. this pin should be decoupled to dvss by capacitors mounted close to the device pins. 6 cdata ip c-bus ?command data?: se rial data input from the c 7 rdata ts op c-bus ?reply data?: a 3-state c-bus serial data output to the c. this output is hi gh impedance when not sending data to the c 8 - nc reserved ? do not connect this pin 9 dvss pwr digital ground 10 sclk ip c-bus ?serial clock? input from the c 11 sysclk2 op synthesised digital system clock output 2 12 csn ip c-bus: the c-bus chip select input from the c - there is no internal pull-up on this input 13 - nc reserved ? leave unconnected 14 - nc reserved ? leave unconnected 15 - nc reserved ? leave unconnected 16 - nc reserved ? leave unconnected 17 - nc reserved ? leave unconnected 18 - nc reserved ? leave unconnected 19 dvss pwr digital ground 20 irqn op c-bus: a 'wire-orable' output for connection to the interrupt request input of the host. pulled down to dv ss when active and is high impedance when inactive. an external pull-up resistor (r1) is required. 21 vdec pwr internally generated 2.5v digi tal supply voltage. must be decoupled to dv ss by capacitors mounted close to the device pins. no other connections a llowed, except for optional connection to rfv dd . 22 rxena op rx enable ? active lo w when in rx mode ($c1:b0 = 1) 23 - nc reserved ? leave unconnected 24 - nc reserved ? leave unconnected 25 sysclk1 op synthesised digital system clock output 1
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 8 d/148/6 48-pin q3/l4 signal name type CMX148 description 26 dvss pwr digital ground 27 txena op tx enable ? active low when in tx mode ($c1:b1 = 1) 28 disc ip discriminator am plifier inverting input 29 discfb op discriminator amplifier feedback 30 sig ip signal input amplifier inverting input 31 sigfb op signal input amplifier feedback 32 micfb op microphone amplifier feedback 33 mic ip microphone amplifier inverting input 34 avss pwr analogue ground 35 mod1 op modulator 1 output 36 mod2/sigout op modulator 2 output (tx) or external sub-audio output (rx) 37 vbias op internally generated bias voltage of about av dd /2, except when the device is in ?powersave? mode when v bias will discharge to av ss . must be decoupled to av ss by a capacitor mounted close to the device pi ns. no other connections allowed. 38 audio op audio output 39 adc1 ip auxiliary adc input (1) 40 adc2 ip auxiliary adc input (2) 41 adc3 ip auxiliary adc input (3) 42 adc4 ip auxiliary adc input (4) each of the two adc blocks can select its input signal from any one of these input pins, or from the mic, sig or disc input pins. see section 8.1.5 for details. 43 avdd pwr positive 3.3v supply rail for the analogue on-chip circuits. levels and thresholds within the device are proportional to this voltage. this pin should be decoupled to av ss by capacitors mounted close to the device pins. 44 dac1 op auxiliary dac output 1/ramdac 45 dac2 op auxiliary dac output 2 46 avss pwr analogue ground 47 dac3 op auxiliary dac output 3 48 dac4 op auxiliary dac output 4 e xposed m etal p ad substrate ~ on this device, the central metal pad (which is exposed on q3 packages only) may be electrically unconnected or, alternatively, may be connected to analogue ground (avss). no other electrical connections are permitted. notes: ip = input (+ pu/pd = internal pull-up/pull-down resistor) op = output bi = bidirectional ts op = 3-state output pwr = power connection nc = no connection - should not be connected to any signal
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 9 d/148/6 4. external components CMX148 (q3/l4) dvss vdec xtal/clock xtaln dvdd cdata rdata dvss csn sysclk2 sclk 13 20 nc dvss irqn 1 8 2 3 4 5 6 7 9 10 12 15 16 17 18 nc nc 19 21 vdec rxena 23 24 22 nc nc 14 nc 26 28 29 30 31 32 33 34 36 35 nc nc sysclk1 dvss txena mod2/sigout mod1 avss mic micfb discfb disc sigfb sigin 38 39 40 48 47 45 dac4 dac2 46 avss 44 dac3 dac1 43 avdd adc2 adc1 audio vbias 11 25 41 42 adc4 adc3 nc c16 r10 r9 c15 mic in sig in tx enable r7 r8 c14 r5 r6c12 c13 c11 av ss mod 2 av ss mod 1 dv ss c24 c23 + dv ss dv ss dv dd disc in sys clock 1 dv ss dv dd cdata rdata sclk dv ss csn sysclk2 irqn rx enable av ss auxiliary multiplexed adc inputs av ss audio op av dd auxiliary dacs av ss av ss c3 c2 c1 r2 r3 r4 c6 c7 c5 r1 x1 sigout av dd c18 av ss av ss dv ss dv ss dv ss dv dd c19 c17 c20 c21 c22 + + c8 c9 27 37 figure 2 recommended external components r1 100k c1 18pf c11 see note 5 c21 10nf r2 100k c2 18pf c12 180pf c22 10nf r3 100k c3 10nf c13 see note 5 c23 10nf r4 100k c4 not used c14 180pf c24 10f r5 see note 2 c5 1nf c15 see note 5 r6 100k c6 100pf c16 180pf r7 see note 3 c7 100nf c17 10f r8 100k c8 100pf c18 10nf x1 3.6864mhz r9 see note 4 c9 100pf c19 10nf see note 1 r10 100k c10 not used c20 10f resistors 5%, capacitors and inductors 20% unless otherwise stated. notes: 1. x1 can be a crystal or an external clock gener ator; this will depend on the application. the tracks between the crystal and the device pins should be as short as possible to achieve maximum stability and best start up performance. by default, a 3.6864mhz clock is selected, other values could be used if the various internal clock di viders are set to appropriate values. 2. r5 should be selected to provide the desired dc gain (assuming c11 is not present) of the disc input, as follows: ? gain disc ? = 100k / r5 the gain should be such that the re sultant output at the discfb pin is within the input signal range specified in 7.14.2. 3. r7 should be selected to provide the desired dc gain (assuming c13 is not pr esent) of the sig input as follows: ? gain sig ? = 100k / r7
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 10 d/148/6 the gain should be such that the re sultant output at the sigfb pin is within the input signal range specified in 7.14. 4. r9 should be selected to provide the desired dc gain (assuming c15 is not pr esent) of the mic input as follows: ? gain mic ? = 100k / r9 the gain should be such that the re sultant output at the micfb pin is within the input signal range specified in 7.14.1. for optimum performance with low signal microphones, an additional external gain stage may be required. 5. c11, c13 and c15 should be selected to maintain the lower frequency roll-off of the mic, sig and disc inputs as follows: c11 1.0f ? gain disc ? c13 1.0f ? gain sig ? c15 30nf ? gain mic ? 6. sig and sigfb connections allow the user to have an additional signal input (usually assigned to the external signalling). component connections and values are as for the respective disc and mic networks. if this input is not requir ed, the sig pin should be connected to avss. 7. c5 (audio output) should be increased to 1. 0f if frequencies below 300hz need to be used on this pin. 8. a single 10f electrolytic capacitor (c24, fi tted as shown) may be used for smoothing the power supply to both vdec pins, providing they are connected together on the pcb with an adequate width power supply trace. alternativ ely, separate smoothing capacit ors should be connected to each vdec pin. high frequency decoupling capacitors (c3 and c23) must always be fitted as close as possible to both vdec pins.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 11 d/148/6 5. pcb layout guidelines and power supply decoupling CMX148 (q3/l4) dvss vdec dvdd dvss 13 20 dvss 1 8 2 3 4 5 6 7 9 10 12 15 16 17 18 19 vdec 23 24 22 14 26 28 29 30 31 32 33 34 36 35 dvss avss 38 39 40 48 47 45 46 avss 44 43 avdd vbias 11 25 41 42 dv ss c24 c23 + dv ss dv ss dv ss dv dd dv ss av ss av ss av ss c3 c7 av dd c18 av ss av ss dv ss dv ss dvss c19 c17 c20 c21 c22 + + av ss digital ground plane analogue ground plane 27 21 37 figure 3 power supply and decoupling component values as per figure 2. notes: it is important to protect the analogue pins from extraneous inband noise and to minimise the impedance between the device and the supply and bias decoupling capacitors. the decoupling capacitors c3, c7, c18, c19, c21, c22, c24 and c25 should be as cl ose as possible to the device. it is therefore recommended that the printed circuit board is la id out with separate ground planes for the av ss and dv ss supplies in the area of the cmx 148, with provision to make links between them, close to the device. use of a multi-layer printed circuit board will facilitate the provision of ground planes on separate layers. v bias is used as an internal reference for detecti ng and generating the various analogue signals. it must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. if v bias needs to be used to set the discriminat or mid-point reference, it must be buffered with a high input impedance buffer. the single ended microphone input and audio output must be ac coupled (as shown), so that their return paths can be connected to av ss without introducing dc offsets. fu rther buffering of the audio output is advised. the crystal x1 may be replaced with an external clock source.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 12 d/148/6 6. general description the CMX148 is intended for use in half-duplex analogue tw o way mobile radio or family radio equipment and is particularly suited to both the pmr mark ets and enhanced murs/gmrs/frs with gps terminal designs. the CMX148 provides radio signal filter ing, encoder and decoder functions for: audio, inband tones, dtmf, and msk/ffsk data, permitting simple to sophisticated levels of tone control and data transfer. a flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals. the CMX148 includes a crystal clock generator, with a buffered output, to provide a common system clock if required. a block diagram of the CMX148 is shown in figure 1. the signal processing blocks can be individually assigned to either of two signal processing paths, which in turn, can be routed from any of the three audio/discrim inator input pins. this allows for a very flexible routing architecture and allows the facility for di fferent processing blocks to act on different analogue inputs. additional filtering is included to support host-generat ion or detection of sub-audible ctcss/dcs tones. tx functions: o single/dual microphone or external signalling i nputs with input amplifier and programmable gain adjustment o filtering selectable for 12.5khz and 25khz channels o selectable pre-emphasis o selectable compression o selectable frequency inversion voice scrambling o selectable audio processing order o 2-point modulation outputs with programmable level adjustment o filtering for external ctcss or dcs signals o programmable audio tone generator (for custom audio tones) o programmable dtmf generator o 1200/2400 baud msk/ffsk modem and data packet encoder (suitable for text messaging/paging, caller identificati on, caller location, digital poll of remote radio location, gps information in nmea 0183 format, data transfer, mpt1327 etc.) incorporating interleaving, fec, crc and data scrambling o tx enable output rx functions: o single/dual demodulator inputs with input amplifier and programmable gain adjustment o audio-band and sub-audio rejection filtering o selectable de-emphasis o selectable expansion o selectable frequency inversion voice de-scrambling o selectable audio processing order o software volume control o filtering for external ctcss or dcs signals o dtmf decoder o 1200/2400 baud msk/ffsk data packet decoder with automatic bit rate recognition, 16-bit frame sync detection, error correction, data de-scrambler and packet disassembly o rx enable output auxiliary functions: o 2 programmable system clock outputs o 2 auxiliary adcs with selectable input paths o 4 auxiliary dacs, one with built-in programmable ramdac interface: o c-bus, 4-wire high-speed synchronous serial command/data bus o open drain irq to host
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 13 d/148/6 7. detailed descriptions 7.1. device identification code following a power-on or reset (see 8.1.1), the device will report the de vice identification code in the tone status register ($cc) to indicate that it is operational. 7.2. xtal frequency the CMX148 is designed to work with a xtal of 3.6864m hz. if this default configuration is not used, then program block 3 (see 8.2.4) should be loaded with the correct val ues to ensure that the device will work to specification with the user specified clock frequency. a table of common values can be found in table 1. note the maximum xtal frequency is 12.288mhz , although an external clock source of up to 24.576mhz can be used. the register values in table 1 are shown in hex (how ever not all bits are relevant, see program block 3 for details), the default settings are shown in bold, and the settings which do not give an exact setting (but are within acceptable limits) are in italics. the new p3 .2-3 settings take effect following the write to p3.3 (the settings in p3.4-7 are implemented on a change to rx or tx mode). table 1 xtal/clock frequency settings for program block 3 program block entry external frequency source (mhz) 3.6864 6.144 9.216 12.0 12.8 16.368 16.8 19.2 p3.2 gp timer $01c $018 $018 $019 $019 $018 $019 $018 p3.3 idle vco output and aux clk divide $084 $088 $08c $10f $110 $095 $115 $099 p3.4 ref clk divide $030 $040 $060 $07d $0c8 $155 $15e $0c8 p3.5 pll clk divide $280 $200 $200 $200 $300 $400 $400 $200 p3.6 vco output and aux clk divide $13c $140 $140 $140 $140 $140 $140 $140 p3.7 rx or tx internal adc/dac clk divide $008 $008 $008 $008 $008 $008 $008 $008 7.3. host interface a serial data interface (c-bus) is used for comm and, status and data transfe rs between the CMX148 and the host c; this interface is compatible with mi crowire and spi. interrupt signals notify the host c when a change in status has occurred and the c should read the status register across the c-bus and respond accordingly. interrupts only occur if the appropriate mask bit has been set. see section 8.1.3. the CMX148 will monitor the state of the c-bus registers that the hos t has written to every 250s (the c- bus latency period) hence it is not advisable for the host to make successive writes to the same c-bus register within this period. to minimise activity on the c-bus interface, optim ise response times and ensure reliable data transfers, it is advised that the irq facility be utilised (using the ir q mask register, $ce). it is permissible for the host to poll the irq pin if the host c does not support a fu lly interrupt-driven architecture. this removes the need to continually poll the c-bus status register ($c6) for status changes. the c-bus block provides for the transfer of dat a and control or status information between the CMX148?s internal registers and the hos t c over the c-bus serial interf ace. each transaction consists of a single address byte sent from the c which may be followed by one or more data byte(s) sent from the c to be written into one of the CMX148?s write only registers, or one or more data byte(s) read out from one of the CMX148?s read only registers, as illustrated in figure 4.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 14 d/148/6 data sent from the c on the cdata line is clo cked into the CMX148 on the rising edge of the sclk input. rdata sent from the CMX148 to the c is va lid when sclk is high. the csn line must be held low during a data transfer and kept high between transfers . the c-bus interface is compatible with most common c serial interfaces and may also be eas ily implemented with general purpose c i/o pins controlled by a simple software routine. the number of data bytes following an address byte is dependent on the value of the address byte. the most significant bit of the address or data ar e sent first. for detailed timings see section 9.2. note that, due to internal timing constraints, there may be a delay of up to 250s between the end of a c-bus write operation and the device reading the data fr om its internal register. ensure that this c-bus latency time (up to 250s) is observed when writing multip le commands to the same c-bus register. c-bus write: see note 1 see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 7 6 ? 0 7 ? 0 msb lsb msb lsb msb lsb address/command byte upper 8 bits lower 8 bits rdata high z state c-bus read: see note 2 csn sclk cdata 7 6 5 4 3 2 1 0 msb lsb address byte upper 8 bits lower 8 bits rdata 7 6 ? 0 7 ? 0 high z state msb lsb msb lsb data value unimportant repeated cycles either logic level valid (and may change) either logic level valid (but must not change from low to high) figure 4 c-bus transactions notes: 1. for command byte transfers only the fi rst 8 bits are transferred ($01 = reset). 2. for single byte data transfers only the first 8 bits of the data are transferred. 3. the cdata and rdata lines are never active at the same time. the address byte determines the data direction for each c-bus transfer. 4. the sclk input can be high or low at the start and end of each c-bus transaction. 5. the gaps shown between each byte on the cda ta and rdata lines in the above diagram are optional, the host may insert gaps or concatenate the data as required.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 15 d/148/6 7.4. device control the CMX148 can be set into many modes to suit the environment in which it is to be used. these modes are described in the following sections and are programm ed over the c-bus: either directly to operational registers or, for parameters that are not likely to change during operation, via the programming register ($c8). for basic operation: 1. enable the relevant hardware sections via the power down control register 2. set the appropriate mode registers to the des ired state (audio, inband, sub-audio, data, etc.) 3. select the required signal routing and gain 4. use the mode control register to place the device into rx or tx mode to conserve power when the devic e is not actively processing an analogue signal, place the device into idle mode. additional powersaving can be achieved by disabling the unused hardware blocks, however, care must be taken not to disturb any sect ions that are automatically controlled. see: o powerdown control - $c0 write o mode control ? $c1 write 7.4.1. signal routing the CMX148 offers a very flexible routing architec ture, with three signal inputs, two separate signal processing paths and a selection of two modulator out puts (to suit 2-point as well as i/q modulation schemes) and a single audio output. each of t he signalling processing blocks can be independently routed from either of the two input blocks (input1 or input2), which c an be routed from any of the three input signal amplifiers. the audio/voice processing blocks are always routed from input1. the outputs from signal processing blocks are determined by the settings of the auxadc and tx mod mode register in tx mode. in tx mode, an externally generated sub-audio or in -band signal may be routed via input2. the signal can be appropriately filtered and mixed with the in-band signalling and presented at the mod1 and/or mod2 outputs. in rx mode, sub-audio signalling or in-band signalling can be recovered from the input signal, routed via input1 or input2, and presented on the mod2 output.. see: o input gain and output signal routing - $b1 write o auxadc and tx mod mode - $a7 write o mode control ? $c1 write
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 16 d/148/6 flexible packet ffsk/msk/ fsk modem ctcss external sub-audio filtering dcs bpf data modem in-band signalling dtmf de- emphasis expander de- scrambler channel filter audio processing receive functions sig mic disc v mux $c1 b7 hpf mux $c1 b11 hpf audio routing $b1 b6 v v input2 $b1 b15-13 input1 $b1 b12-10 free format mux $c1 b4 mux $b1 b3,2 mux $b1 b5,4 audio gain $b0 b3-0 data modem compressor scrambler inband signalling programmable tone dtmf external sub-audio filtering ctcss dcs audio processing transmit functions pre- emphasis channel filtering soft limiter tx mod mode $a7 b12,13 mux $c1 b6,5 mux $c1 b14-2 free format ffsk/msk/ fsk modem output1 output2 flexible packet mod2 gain $b0 b10-8 mod1 gain $b0 b14-11 mux $b1 b9,8 mux $b1 b7 output1 mux $c1 b6,5 mux $c1 b7 audio mod2/ sigout mod1 bias bias bias figure 5 signal routing the analogue gain/attenuation of each input and output can be set individually, with additional fine gain control available via the programming register. see: o analogue output gain - $b0 write o input gain and output signal routing - $b1 write 7.4.2. mode control the CMX148 operates in one of three modes: o idle o rx o tx at power-on or following a reset or general reset, t he device will automatically enter idle mode, which allows for the maximum powersaving whilst still retain ing the capability of monito ring the four adc inputs (if enabled). it is only possible to write to the programming register whilst in idle mode. see: o mode control ? $c1 write
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 17 d/148/6 7.5. audio functions the audio signal can be processed in several wa ys, depending on the implementation required, by selecting the relevant bits in the audio control ? $c2 write regist er. in both rx and tx modes, a selectable channel filter to suit either the 12.5khz or 25khz tia / etsi channel mask can be selected. this filter also incorporates a soft limiter to reduce t he effects of over-modulati on. other features include 300hz hpf, pre- and de-emphasis, companding and frequency inversion scrambling, all of which may be individually enabled 1 . the order in which these features are ex ecuted is selectable to ensure compatibility with existing implementations and prov ide optimal performance (see section 8.2.5). the alternate settings shown in section 8.2.5 may provide better performanc e than the default configuration 7.5.1. audio receive mode the CMX148 operates in half-duplex, so whilst in re ceive mode the transmit path (mic input and mod1/2 amplifiers) can be disabled and powered down if requir ed. the audio output signal level is equalised (to v bias ) before switching between the audio port and the modulator ports, to minimise unwanted audible transients. the off/powersave level at mod1/2 outputs is the same as the v bias pin, so the audio output level must also be at this level before switching. see: o audio control ? $c2 write receiv ing audio band signals when a voice-based signal is being received, it is up to the host c, in response to signal status information provided by the CMX148, to control mu ting/enabling of the audio signal to the audio output. the discriminator path through the device has a progr ammable gain stage. whilst in receive mode this should normally be set to 0db (the default) gain. receive filtering the incoming signal is filtered, as shown in figure 7 (with the 300hz hpf also active), to remove sub- audio components and to minimise high frequency noise. when appropriate, the audio signal can then be routed to the audio output. separate se lectable filters are available for: ? 300hz high pass (to reject sub-audible signalling) ? 2.55khz low pass (for 12.5khz channel operation) ? 3.0khz low pass (for 25khz channel operation) note that with no filters selected, the low frequency response ex tends to below 5hz at the low end but still rolls off above 3.3khz at the top end. the cut-off point of the 300hz hpf can be set to ei ther 280hz, 300hz or 320hz by setting the relevant bits of program block p2.5, as shown in figure 6. 1 the typical responses shown in figure 7, figure 10, figure 11 were recorded using the ev1480 evkit, disc to audio and mod1.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 18 d/148/6 -50 -40 -30 -20 -10 0 10 100 1000 frequency (hz) gain (db) flat_300 flat_280 flat_320 250hz 280hz 300hz 320hz figure 6 adjustable hpf response af response - rx mode 25khz channel filter & 300hz hpf -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 frequency (hz) amplitude (db) 25khz & hpf enabled (c2h=0c00h) 25khz ch tem plate (tia/eia) 12.5khz ch tem plate (tia/eia) no filters (c2h=0000h) 300hz hpf -60 db/decade (-50 db) 20khz -100 db/decade (-82.5 db) ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4001h 250h z 3khz 2.55khz 300h z +1db/-3db wrt ref. figure 7 rx 25khz channel audio filter frequency response
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 19 d/148/6 af response - rx mode 12.5khz channel filter & 300hz hpf -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 frequency (hz) amplitude (db) 12.5khz & hpf enabled (c2h=1400h) 25khz ch tem plate (tia/eia) 12.5khz ch tem plate (tia/eia) no filters (c2h=0000h) 12.5khz only (c2h=1000h) -60 db/decade (-50 db) 20khz -100 db/decade (-82.5 db) ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4001h 250h z 3khz 2.55khz 300h z +1db/-3db wrt ref. figure 8 rx 12.5khz channel audio filter frequency response af response - rx mode de-emphasis tia/eia-603 compliance -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 10 100 1000 10000 100000 frequency (hz) amplitude (db) 12.5khz & hpf enabled (c2h=3400h) 12.5khz enabled (c2h=3000h) tem plate (tia/eia) ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4001h 2.55khz 300h z -6db/octave +11.4db figure 9 de-emphasis 12.5khz
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 20 d/148/6 de-emphasis optional de-emphasis at -6db per oc tave from 300hz to 3000hz (shown in figure 9) can be selected, to facilitate compliance with tia/eia-603, en 300 086, en 301 025 etc. the template shows the +1 and - 3db limits. rx companding (expanding) the CMX148 incorporates an opti onal syllabic compandor in both transmit and receive modes. this expands received audio band signals t hat have been similarly compressed in the transmitter to enhance dynamic range. see the next section and: o audio control ? $c2 write audio de-scrambling the CMX148 incorporates an optional frequency inve rsion de-scrambler in receive mode. this de- scrambles received audio band signal s that have been scrambled in the transmitter. the inversion frequency defaults to 3300hz, but maybe modified by writing to p4.8. see: o audio control ? $c2 write 7.5.2. audio transmit mode the device operates in half-duplex, so when the device is in transmit mode the receive path (discriminator and audio output amplifiers) should be disabled, and can be powered down, by the host c. two modulator outputs with independently programmable gains are provided to facilitate single or two- point modulation, separate sub-audi o and audio band outputs. if one of t he modulator outputs is not used it can be disabled to conserve power. to avoid spurious transmissions when changing from rx to tx, the mod1 and mod2 outputs are ramped to the quiescent modulator output level, v bias before switching (if enabled by b7 of the analogue gain register, $b0). similarly, when starting a transmi ssion, the transmitted signal is ramped up from the quiescent v bias level and when ending a transmission the transmitted signal is ramped down to the quiescent v bias level. the ramp rates are set in the pr ogram block p4.6. when the modulator outputs are disabled, their outputs will be set to v bias . when the modulator output drivers are powered down, their outputs will be floating (high impedance), so the rf modulator will need to be turned off. for all transmissions, the host c must only enable signals after the appropriate data and settings for those signals are loaded into the c-bus registers. as soon as any signalling is enabled the CMX148 will use the settings to control the way information is transmitted. a programmable gain stage in the microphone input path facilitates a host controlled vogad capability, or an internal agc function may be used. see: o audio control ? $c2 write o auxadc and tx mod mode - $a7 write o input gain and output signal routing - $b1 write processing audio signals for transmission ov er analogue channels the microphone input(s), with programmable gain, can be selected as the audio input source. pre- emphasis is selectable with either of the two analogue tx audio filters (for 12.5khz and 25khz channel spacing). these are designed for use in en 300 086, tia/eia-603 or en 301 025 compliant applications. when the 300hz hpf is enabled, it will attenuate s ub-audio frequencies below 250hz by more than 33db with respect to the signal level at 1khz. these filters, together with a built in limiter , help ensure compliance with en 300 086 and en 301 025 (25khz and 12.5khz channel spacing) when levels and gain settings are set up correctly in the target system.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 21 d/148/6 af response - tx mode 25khz channel filter & 300hz hpf soft limiter -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 frequency (hz) amplitude (db) 25khz & hpf enabled (c2h=0c00h) 25khz ch tem plate (etsi) no filters (c2h=0000h) 300hz hpf (c2h=0400h) -14 db/octave (-50 db) 40khz ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4002h 3khz 300h z 250h z +1db/-3db wrt ref. 6khz figure 10 tx channel audio filter response and template (etsi) af response - tx mode 12.5khz channel filter & 300hz hpf soft limiter -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 frequency (hz) amplitude (db) 12.5khz & hpf enabled (c2h=1400h) 25khz ch tem plate (tia/eia) 12.5khz ch tem plate (tia/eia) no filters (c2h=0000h) 12.5khz only (c2h=1000h) -60 db/decade (-50 db) 20khz -100 db/decade (-82.5 db) ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4002h 250h z 3khz 2.55khz 300h z +1db/-3db wrt ref. figure 11 tx channel audio filter response and template (tia) the characteristics of the 12.5khz channel filter fit the template shown in figure 10 and figure 11. this filter also facilitates implement ation of systems compliant with tia/eia-603 ?a? , ?b? and ?c? bands .
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 22 d/148/6 the CMX148 provides selectable pre-emphasis filter ing of +6db per octave from 300hz to 3000hz, matching the template shown af response - tx mode pre-emphasis tia/eia-603 compliance soft limiter -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 10 100 1000 10000 100000 frequency (hz) amplitude (db) 12.5khz & hpf enabled (c2h=3400h) 25khz & hpf enabled (c2h=2c00h) tem plate ((tia/eia) ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4002h 250h z 2.55khz 300h z +6db/octave figure 12 audio frequency pre-emphasis
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 23 d/148/6 af response - tx mode pre-emphasis tia/eia-603 compliance hard limiter -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 10 100 1000 10000 100000 frequency (hz) amplitude (db) 12.5khz & hpf enabled (c2h=3400h) 25khz & hpf enabled (c2h=2c00h) tem plate ((tia/eia) ref. 0dbv rbw 10hz vbw 30hz sweep time: 160 secs c1h 4002h 250h z 2.55khz 300h z +6db/octave figure 13 audio frequency pre-emphasis modulator output routing the sub-audio component can be combined with the audio band signal and this composite signal routed to both mod1 and mod2 outputs, or the sub-audi o and audio band signal can be output separately (sub- audio to mod2 and audio band to mod1), in accordance with the settings of: o auxadc and tx mod mode - $a7 write o input gain and output signal routing - $b1 write alternatively, the combined sub-audio and audio band composite signal can be output on mod1 and mod2 in a phase / quadrature (i/q) format suitable for dire ct upconversion to the final rf signal. due to the nature of the i/q modulation, this mode is only feasible in rf channels / systems which have a maximum frequency deviation of 3khz or less. additional test modes are provided for calibrating external circuits. tx i/q mode is particularly suitable for data transmission. inputagc an automatic gain control system can be enabled by se tting the relevant bits of the program block p4.9. the setting of the input1 gain stage is recorded when the device enters tx mode and if the signal exceeds the pre-set threshold, the i nput1 gain is automatically reduced in 3.2db steps until it falls within the operational levels or the range of the gain stage is exhausted. when the signal level drops, the gain will be automatically increased in 3. 2db steps at the rate set in p4.9 until the initial values has been reached. for maximum effect the system should be des igned such that the +22. 4db setting of the input1 gain stage achieves the nominal levels. to ensure consistent operation, it is recommended that the input1 gain stage value be re-initialised before entering tx mode. the signal that is used as an input to this process can be selected to be either the: ? output of input1 gain stage ? output of the pre-emphasis filter
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 24 d/148/6 by selecting the relevant bit in p4.9. the pre-em phasis option should only be chosen if this block is actually in use. o input gain and output signal routing - $b1 write o program block 4 ? gain and offset setup tx companding (compressing) the CMX148 incorporates an opti onal syllabic compandor in both transmit and receive mode. this compresses audio band signals before transmissi on to enhance dynamic range. see section 7.5.1 and: o audio control ? $c2 write audio scrambling the CMX148 incorporates an optional frequency inversi on scrambler in transmit mode. this scrambles audio band signals, to be de-scrambled in the receiver . the inversion frequency defaults to 3300hz, but may be modified by writing to p4.8. see: o audio control ? $c2 write audio compandor the compandor is comprised of a compressor and an expandor. the compressor?s function is to reduce the dynamic range of a given signal by attenuating larger amplitudes wh ile amplifying smaller amplitudes. the expandor?s function is to expand the dynamic range of a given signal by attenuating small amplitude signals (e.g. noise) while amplifying large amplitude si gnals. the compressor is used prior to transmission and the expandor is used in the receiver. hence, using a compandor will enhance performance in a communication system by transmitting a compressed si gnal, which is less likely to be corrupted by noise, and then at the receiver expanding the compressed signal, which will push the noise picked up during transmission down further. the CMX148 uses a ?syllabic compandor.? this type of compandor, as opposed to the instantaneous compandor (e.g. /a-law pcm), responds to changes in the average envelope of the signal amplitude according to a syllabic time constant . typically the steady state output for the compressor is proportional to the square root of the input signal. ie:, for a 2 db change in input signal, the output change will be 1 db. generally for voice communication systems a compressor is expected to have an input dynamic range of 60 db, providing an output dynamic range of 30 db. the expandor does the inverse.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 25 d/148/6 figure 14 expandor transient response figure 15 compressor transient response
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 26 d/148/6 7.6. external sub-audio signalling filtering for sub-audio signalling is available in the audio band below 260hz. when sub-audio signalling is enabled, the 300hz hpf in the audio section should also be enabled to remove the sub-audio signalling from the audio signal (in both tx and rx). in tx mode, the external sub-audio signal should be r outed to input2 (by conventi on, from the sig input), and the filter selected using b6-5 of the mode register, $c1. this signal will then be summed with the current in-band signal according to the settings in the adc register, $a7. the level of this signal may be adjusted by using the input2 coar se and fine gain settings ($b0 and p4.2) or the tx sub-audio level control (p2.0). this signal path is dc?coupled. in rx mode, the input signal can be routed from either input1 or input2 depending on the setting of the mode register, $c1, bit 7 and is then filtered according to the settings of b6-5 of the mode register and presented at the mod2 output. suitable external switchi ng is required if this output is also used in tx mode. to assist in compensating for the different levels expected for the sub-audio signalling compared with the in-band signals, the ctcss and dcs filters exhibit 6db of attenuation in tx and 12db of gain in rx. the dcs filter is a 4-pole bessel f ilter with a ?3db point at 134hz. the ctcss filter is a 6-pole cauer filter with a ?3db point at 260hz. setting both b6-5 to 1 enables a straight-through path which exhibits a roll off at 2700hz. see: o analogue output gain - $b0 write o mode control ? $c1 write tx external sub-audio frequency response -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 frequency (hz) gain (db) ctcss filter dcs filter through filter ctcss filter cut-off frequency dcs filter cut-off frequency through filter cut-off frequency 260hz 134hz 2.7khz figure 16 external signalling filter response 7.7. inband signalling
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 27 d/148/6 the CMX148 supports dtmf signalling and generati on of a user-programmable audio tone between 288hz and 3000hz. note that if tones below 400hz are used, sub-audio signalling should be disabled and the 300hz hpf disabled. selection of the inband signalling mode is performed by bi ts 11-8 of the mode regist er ($c1). detection of the selected inband signalling mode can be performed in parallel with voice or data reception. see: o mode control ? $c1 write o tx inband tones - $c3 write o tone status - $cc read o audio tone - $cd: write 7.7.1. receiving dtmf tones dtmf tone detection may be enabled in the mode regi ster ($c1) in parallel with other inband tone modes (however, this is not recommended due to t he increased likelihood of false detects). when a dtmf tone has been detected, b10 of t he tone status register ($cc) and b12 of the irq status register, $c6, will be set. this value will over-write any ex isting inband tone value that may be present. the dtmf detector returns the values shown below in table 2. 7.7.2. transmitting dtmf tones the dtmf signals to be generated are defined in the tx tone register ($c3). single tones and twist (lower frequency tone reduced by 2db) can be enabled by se tting the appropriate bit in the $c3 register to 1. the dtmf level is set in program block p1.0. the dtmf tones must be transmitted on their own, the host c must disable audio band signals prior to in itiating transmission of the dtmf tones and (if required) restore the audio band signals after the dtmf transmission is complete. table 2 shows the dtmf tone pairs, together with the values for progra mming the ?tone pair? field of the txtone register. table 2 dtmf tone pairs tone code (hex) key pad position low tone (hz) high tone (hz) 1 1 697 1209 2 2 697 1336 3 3 697 1477 4 4 770 1209 5 5 770 1336 6 6 770 1477 7 7 852 1209 8 8 852 1336 9 9 852 1477 a 0 941 1336 b * 941 1209 c # 941 1477 d a 697 1633 e b 770 1633 f c 852 1633 0 d 941 1633 note: only the underlined tone is generat ed when the 'single tone' bit is enabled. 7.7.3. transmitting audio tones see section 8.1.29 audio tone - $cd: write 7.8. msk/ffsk data modem the CMX148 supports both 1200 and 2400 baud msk/ffsk dat a modes. in rx mode, the device can be set to look for either of the msk or ffsk modes, however, once a valid mode has been found, it will stay in that mode until the host resets it.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 28 d/148/6 see: o mode control ? $c1 write o modem control - $c7 write o rx data 1 and 2 - $c5 and $c9 read o tx data 1 and 2 - $ca and $cb write 7.8.1. receiving msk/ffsk signals the CMX148 can decode incoming msk/ffsk signal s at either 1200 or 2400 baud data rates, automatically detecting the rate from the received signal. alternativel y, a control word may set the baud rate, in which case the device only responds to si gnals operating at that rate. the form of msk/ffsk signals for these baud rates is shown in figure 17. the received signal is filtered and data is extracted with the aid of a p ll to recover the clock from the serial data stream. the recovered data is stored in a 2- or 4-byte buffer (grouped into 16-bit words) and an interrupt issued to indicate received data is ready . data is transferred over the c-bus under host c control. if this data is not read bef ore the next data is decoded it will be ov erwritten and it is up to the user to ensure that the data is transferred at an adequate rate following data ready being flagged, see table 5. the msk/ffsk bit clock is not output externally. the extracted data is compared with the 16-bit programmed frame sync pattern (preset to $cb23 following a reset command). an interrupt will be fl agged when the programmed frame sync pattern is detected or when the following frame head is decoded, see section 7.9.3. the host c may stop the frame sync search by disabling the msk/ffsk dem odulator. once a valid frame sync pattern has been detected, the frame sync search al gorithm is disabled; it may be re -started by the host disabling the modem control bits of the mode r egister ($c1:b2,3) and then re-enabli ng them (taking note of the c-bus latency time). if the CMX148 has been set to decode a frame head befor e interrupting, it will check the crc portion of the frame head control field. if this indicates a co rrupt frame head then a search for a new frame sync pattern will be automatically restarted. ffsk may be transmitted in conjunction with a ct css or dcs sub-audio component. the device will handle the sub-audio signals as previ ously described. if a sub-audio signal turns off during reception of ffsk, it is up to the host c to turn off the dec oding as the device will continue receiving and processing the incoming signal until commanded otherwise by the host c. the host c must keep track of the message length or otherwise determine the end of reception (e.g. by using sub-audio information to check for signal pres ence) and disable the demodulator at the appropriate time. note that when using packets with embedded size information, the CMX148 will indicate when the last data block has been received. 7.8.2. transmitting msk/ffsk signals the msk/ffsk encoding operates in accordance with the bit settings in the modem control register ($c7). when enabled the modulator will begin transmitting data using the settings and values in program block 0 (bit sync and frame sync patterns), the m odem control register and t he tx data registers. therefore, these registers should be programmed to the required values before transmission is enabled. the CMX148 generates its own internal data clock and converts the binary data into the appropriately phased frequencies, as shown in figure 17 and table 3. the binary data is taken from tx data 1 and 2 registers ($ca and $cb), most significant bit first. the following data words must be provided over the c- bus within certain time limits to ensure the selected baud rate is maintained. the time limits will be dependent on the data coding being used, see table 5. rx sign a li/p logic '1' logic '0' 2400 b a ud logic '1' logic '0'
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 29 d/148/6 r x s i g n a l i / p 1 2 0 0 b a u d l o g i c ' 1 ' l o g i c ' 0 ' l o g i c ' 1 ' l o g i c ' 0 ' figure 17 modulating waveforms for 1200 and 2400 baud msk/ffsk signals the table below shows the combinations of frequencie s and number of cycles to represent each bit of data, for both baud rates. table 3 data frequencies for each baud rate baud rate data frequency number of cycles 1200baud 1 1200hz one 0 1800hz one and a half 2400baud 1 1200hz half 0 2400hz one note: ffsk may be transmitted in conjuncti on with a ctcss or dcs sub-audio component. 7.9. msk/ffsk data packetising the CMX148 has extensive data packe tising features that can be c ontrolled by the modem control register ($c7). the CMX148 can packetise data in a va riety of formats so the user can have the optimum data throughput for various signal-to-noise ratios. data is transferred in packets or frames, each frame is made up of a frame head followed by any associated user data. the frame head is composed of a 16- bit bit sync and 16-bit frame sync pattern immediatel y followed by a 4-byte control field. the 4 bytes start with an 8-bit address followed by 1 byte carryi ng information about the format of the following data block. the next byte indicates the size of t he packet or can be used freely, depending on the format selected. the last byte is a checksum to detect if any of the 4 frame h ead bytes has been corrupted. 7.9.1. tx hang bit when transmitting msk/ffsk data of types 0, 2 or 3, the user should ensure that the data is terminated with a hang bit. to do this, the host must set the 'last data' bit in the modem control register ($c7) after the last data word has been loaded into the tx data 1 register ($ca), as described in section 8.1.27. this will append a hang bit onto the end of the current word and will stop modulating after the hang bit has been transmitted. it will also generate an interrupt (if enabled) when the hang bit has left the modulator. 7.9.2. frame format ---------------------------------frame head--------------------------------- ---sync field--- ------------------control field------------------ --------data block-------- bit sync frame sync address byte format byte size^ or user byte check- sum a data bytes check- sum b* 16 bits 16 bits byte 1 byte 2 byte 3 byte 4 * checksum b not applied to all data block types ^ byte 3 is only reserved on sized data blocks. the data block is made up from the user data. this consists of a variable number of data bytes optionally encoded to ensure secure delivery over a r adio channel to the receiver. checksum b is only applied at the end of sized data blocks, the receiver can then detect if any of the user data has been corrupted. checksum b is composed of 16 bits for messages 16 bytes and 32 bits for longer messages. 7.9.3. frame head in frame formats 3, 4 and 5, the frame head allo ws the receiver to detect and lock on to msk/ffsk signals, provides basic addressing to screen out unwanted messages and indicates the format, coding and length of any following data.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 30 d/148/6 the four control field bytes have fo rward error correction (fec) applied to them in the transmitter, this adds 4 bits to every byte and the receiver can correct errors in the received by tes. the 4 received bytes are then checked for a correct crc, so that co rrupted frame heads can be rejected. if checksum a indicates that the control field byte s are correct, the address (byte 1) is compared with that stored in the msk header address bits of modem address register, $b6 (b15:8). if a match occurs, or if the received address is '40', then an interrupt is raised indicati ng a valid frame head has been received. the frame head is 80 bits long (16 + 16 + {4x12}). the cont ents of a received frame head can be read from rx data registers $c5 and $c9. 7.9.4. data block coding the data block follows the frame head and can be coded with different levels of error correction and detection. the data block format is controlled by t he frame format selected in frame head byte 2, see also section 8.1.24. messages can take the following formats: format: des cription: 0 un-formatted data . this mode should be used with the en_raw bit (b10 of the modem control register) set to 1. the interleave and scrambler settings are ignored. this mode can be useful when interfacing to a system using a different format to those available in the CMX148. in transmit, the device will transmit only the dat a loaded into the txdata 1 register. the host should provide bit sync, frame sync and any requi red formatting data as well as the data block through this register. in receive, the device will search for the pr ogrammed 16-bit frame sync pattern and then output all following data 16 bits at a time. the host w ill have to perform all other data formatting. 1 frame head only . no data block will be added. this format can be useful for indicating channel or user status by using byte 3 and the user bit of the frame head (see section 8.1.24). 2 frame head follow ed by raw data . user data is appended to the frame head in 2-byte units with no formatting or crc added by the CMX148. no size information is set in the frame head and the data block may contain any even number of bytes per frame. 3 frame head followed by fec coded data only . each byte of the user data has 4 bits of fec coding added. no size information is set in the frame head and data block may contain any even number of bytes per frame. no crc is added to the data. 4 frame head followed by fec coded data with an automatic crc at the end of the data block. the number of user data bytes in the fr ame must be set in frame head byte 3. the crc is automatically checked in the receiver and the result indicated to the host c. up to 255 bytes of user data can be sent in each frame using this format. 5 as ?4 above?, with the addition of all data block bytes being interleaved . this spreads the transmitted information over time and helps reduc e the effect of errors caused by fading. interleaving is performed on blocks of 4 bytes, the CMX148 automatically adds and strips out pad bytes to ensure multiples of 4 bytes are sent over the radio channel. notes: ? format 0, 1, 2 and 3 have no size information requirement and do not reserve frame head byte 3. this byte may be freely used by the host c to convey information. in format 4 and 5 this byte must be set to the number of user bytes in the message attached to that frame head ( 255) to allow the receiver to correct ly decode and calculate the crc. ? format 0 data transfers do not use frame heads. in tx the host c must transfer the bit and frame sync data before sending the message data. in rx the host c must decode all data after the frame sync.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 31 d/148/6 table 4 data block formats air time for msk/ffsk message (ms) at at data block format: total over-air bits for an 80-byte message 1200baud 2400baud over air efficiency burst length protection at 1200baud [for 2400baud divide both times by 2] probability of detecting errors 2 720 600 300 89% none zero 3 1040 867 433 62% <0.83ms in any 10ms poor 4 1088 907 453 59% <0.83ms in any 10ms excellent 5 1088 907 453 59% <3.33ms in any 40ms excellent higher levels of error protection have the penalty of adding extra bits to the over air signal and this reduces the effective bit rate. less error protection incr eases the effective bit rate, however in typical radio conditions the penalty is a greater risk of errors leading to repeated messages and a net reduction in effective bit rate compared to using error correction and detection. 7.9.5. crc and fec encoding information for messages with fec coding the following ma trix is used to calculate and decode bytes: data bits fec bits 7 6 5 4 3 2 1 0 3 2 1 0 1 1 1 0 1 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 an 8-bit crc is used in all frame heads wi th the following generator polynomial (gp): x 8 + x 7 + x 4 + x 3 + x 1 + x 0 a 16-bit crc is used at the end of sized data mess ages of up to 16 bytes with the following gp: x 16 + x 12 + x 5 + x 0 a 32-bit crc is used at the end of sized data mess ages of over 16 bytes with the following gp: x 32 + x 31 + x 30 + x 28 + x 27 + x 25 + x 24 + x 22 + x 21 + x 20 + x 16 + x 10 + x 9 + x 6 + x 0 7.9.6. data interleaving the built in msk/ffsk packetising includes the option of interleaving the data in each block (type 5). this, together with forward error correction (fec), r educes the effects of burst errors. interleaving does not add any bits to the message, the packet is asse mbled in 'rows' and then transmitting in 'columns'. data (8 bits) fec (4 bits) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 in the above example the packet is assembled as 4 rows with 12 bits of information per row. when this packet is transmitted, interleaved bits are sent ov er the communication channel in the following order: 0, 12, 24, 36, 1, 13, 25, 37, 2, 14, ... , 33, 45, 10, 22, 34, 46, 11, 23, 35, 47. in the receiving modem the packet is re-assembled (de-interleaved) before error correction. the CMX148 has a built in packet receive modem which is able to recognise (by using the frame head bytes) when the data has been interleaved by the transmitter and w ill decode the data using the correct method. 7.9.7. data scrambling/privacy coding it is preferable for msk/ffsk over-air data to be reasonably random in nature to ensure the receiver can track timing using the bit changes and to smooth t he frequency spectrum. to reduce the possibility of
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 32 d/148/6 user data causing long strings of 1?s or 0?s to be transmitted, a 16-bit data scrambler is provided and operates on all bits after the frame head. the default (standard) setting for this scrambler is with a start code (seed) of $ffff and any receivers with the same seed may decode this data. however, if the transmitter and receiver pre-arrange a different seed then the scrambler will start its sequence in anot her place and any simple receiver that does not know the transmitted seed will not be able to succe ssfully decode the data. this method gives over 65,000 different starting points and the chance of others decoding data successfully is reduced. the CMX148 provides the option of two custom 16-bit words that are programmable by the user in program block p0.4 to p0.7. bits 0 and 1 in t he frame head format byte indicate which setting (standard, seed1, seed2 or none) the following da ta block has been scrambled with, see section 8.1.24. note that a seed of $0000 will effectively turn o ff the scrambler and provide no protection against long sequences of 1?s or 0?s. recept ion of scrambled data will only be su ccessful when the receiving device has been programmed with the correct (identical ) seed to that used by the transmitter. by using this method the CMX148 provides a privac y code that will protect against casual monitoring, however the data is not encrypted and a sophisticated receiver can dec ode the data by using moderately simple decoding techniques. if data encryption is r equired it must be performed by the host c. the scrambler function is controlled by bits 0,1 of the modem control register, $c7. 7.9.8. data buffer timing data must be transferred at the rate appropriate to the signal type and data format. the CMX148 buffers data in two 16-bit registers. the CMX148 will issue interrupts to indicate when data is available or required. the host must respond to these interrupts wi thin the maximum allowable latency for the signal type. table 5 shows the maximum latencies for transferring signal data to maintain appropriate data throughput. table 5 maximum data transfer latency data encoding type max. time to read from or write to data buffer data buffer size 1200 baud 2400 baud 0 13.3ms 6.6ms 2 bytes 1 n/a* n/a* 4 bytes 2 13.3ms 6.6ms 2 bytes 3 20ms 10ms 2 bytes 4 40ms 20ms 4 bytes 5 40ms 20ms 4 bytes * type 1 message is an isolated frame head, there is no subsequent data to load (tx) or read (rx). 7.10. auxiliary adc operation the input to the auxiliary adcs can be independently routed to any of t he signal input pins under control of the auxadc and tx mod mode regi ster, $a7. conversions will be performed as long as a valid input source is selected, to stop the a dc, the input source should be set to ?none?. register $c0, b6, bias, must be enabled for auxiliary adc operation. averaging can be applied to the adc readings by select ing the relevant bits in the auxadc and tx mod mode register, $a7, the length of the averaging is determined by the va lue in the program block (p3.0 and p3.1), and defaults to a value of 0. this is a rolling average system such that a proportion of the current data will be added to the last value. the pr oportion is determined by the value of the average counter in p3.0 and p3.1. for an average value of 0; 50% of the current value will be applied, for a value of 1 = 25%, 2 = 12.5% etc. the maximum useful val ue of this field is 8. averaging will begin with the current value of the auxadc, t herefore it is recommended that the auxadc be enabled for at least one sample (250s) before starting the average process to ensure that its initial value is as expected, otherwise the initial value will default to zero. high and low thresholds may be independently applied to both adc channels (the comparison is applied after averaging, if this is enabled) and an irq generated when either the high threshold is crossed by a rising edge signal or the low threshold is passed by a falling edge signal, which allows the user to implement a selectable degree of hysterisis. the th resholds are programmed via the auxadc threshold register, $b5.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 33 d/148/6 auxiliary adc data is read back in the auxadc data r egister ($a9) and includes the threshold status as well as the actual conversion data (subject to averaging, if enabled). see: o auxadc and tx mod mode - $a7 write o auxadc1 data - $a9 read o auxadc2 data - $aa read o auxadc threshold data - $b5 write 7.11. auxiliary dac/ramdac operation the four auxiliary dac channels are programmed vi a the auxdac control register, $a8. auxdac channel 1 may also be programmed to operate as a ramdac which will automatically output a pre- programmed profile at a programmed rate. the auxdac control register, $a8, with b12 set, controls this mode of operation. the default profile is a raised cosine (see table 9), but this may be over-written with a user defined profile by writing to program block p3.11. the ramdac operation is only available in tx mode and, to avoid glitches in the ramp profile, it is important not to change to idle or rx mode whilst the ramdac is still ramping. the auxdac outputs (avail able on their respective dac pins) hold the user- programmed level during a powersave operation if left enabled, otherwise they will return to zero. note that access to all four auxdacs is controlled by the auxdac control register, $a8, and therefore to update all auxdacs requires four writes to this regist er. it is not possible to simultaneously update all four auxdacs. see: o auxdac control/data - $a8 write
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 34 d/148/6 7.12. digital system clock generator ref clk div /1 to 512 $ac b0-8 pd vco pll div /1 to 1024 $ab b0-9 lpf sysclk1 ref sysclk1 div vco op div /1 to 64 $ab b10-15 sysclk1 pre-clk $ac b11-15 sysclk1 output 384khz-20mhz 48 - 192khz (96khz typ) sysclk1 vco 24.576- 98.304mhz (49.152mhz typ) ref clk div /1 to 512 $ae b0-8 pd vco pll div /1 to 1024 $ad b0-9 lpf sysclk2 ref sysclk2 div vco op div /1 to 64 $ad b10-15 sysclk2 pre-clk $ae b11-15 sysclk2 output 384khz-20mhz 48 - 192khz (96khz typ) sysclk2 vco 24.576- 98.304mhz (49.152mhz typ) ref clk div /1 to 512 p3.4 pd vco pll div /1 to 1024 p3.5 lpf mainclk ref mainclk div vco op div /1 to 64 p3.3 b12-7 p3.6 b12-7 mainclk pre-clk mainclk output 384khz-50mhz (24.576mhz typ) 48 - 192khz (96khz typ) mainclk vco 24.576- 98.304mhz (49.152mhz typ) to internal adc / dac dividers auxadc div p3.3 b6-0 p3.6 b6-0 aux_adc (83.3khz typ) osc 3.0 - 12.288mhz xtal or 3.0 - 24.576mhz clock to rf synthesiser ref clk selection figure 18 digital clock generation schemes the CMX148 includes a 2-pin crystal oscillator circuit. this can either be configured as an oscillator, as shown in section 5, or the xtal input can be driven by an ex ternally generated clock. the crystal (xtal) source frequency can go up to 12.288mhz (clock sour ce frequency up to 24.576mhz), but by default, a 3.6864mhz xtal is assumed for the f unctionality provided in the CMX148.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 35 d/148/6 7.12.1. main clock operation a pll is used to create the main clock (mainclk - nom inally 24.576mhz) for the in ternal sections of the CMX148. at the same time, other internal clocks are generated by division of ei ther the xtal reference clock or the main clock. these internal clocks ar e used for determining the sample rates and conversion times of a-to-d and d-to-a converters, running a gener al purpose timer, the signal processing block. in particular, it should be noted that in idle mode the setting of the gp ti mer divider directly affects the c- bus latency (with the default va lues this is nominally 250 s). the CMX148 defaults to the settings appropriate for a 3.6864mhz xtal, however if other frequencies are to be used (to facilitate commonality of xtals bet ween external rf synthesizers and the CMX148 for instance) then the program block p3.2 to p3.7 will need to be programmed appropriately at power-on. a table of common values is provided in table 1. see: o program block 3 ? auxdac, ramdac and clock control 7.12.2. system clock operation two system clock outputs, sysclk 1 and sysclk2, are available to drive additional circuits, as required. these are phase locked loop (pll) clocks that can be programmed via the system clock registers with suitable values chosen by the user . the system clock pll configure registers ($ab and $ad) control the values of the vco output divider and main divide registers, while the system clock ref. configure registers ($ac and $ae) control the va lues of the reference divider and signal routing configurations. the plls are designed for a reference frequency of 96khz. if not required, these clocks can be independently powersaved. the clock generation scheme is shown in the block diagram of figure 18. note that at power-on, these outputs are disabled. see: o sysclk1 and sysclk2 pll data - $ab, $ad write o sysclk1 and sysclk2 ref - $ac and $ae write 7.13. gpio two pins are provided for control of external har dware. rxena and txena are driven by the device to follow the state of the rx and tx mode bits in the mode register, $c1: $c1 mode: b1 b0 txena rxena idle 0 0 1 1 rx 0 1 1 0 tx 1 0 0 1 reserved 1 1 1 1 7.14. signal level optimisation the internal signal processing of the CMX148 w ill operate with wide dynamic range and low distortion only if the signal level at all stages in the signal pr ocessing chain is kept within the recommended limits. for a device working from a 3.3v 10% supply, the maximum signal level which can be accommodated without distortion is [(3.3 x 90%) ? (2 x 0.3v)] volts p-p = 838mvrms, assuming a sine wave signal. compared to the reference level of 308mvrms, this is a signal of +8.69db. this level should not be exceeded at any stage. 7.14.1. transmit path levels for the maximum signal out of the mod1 and mod2 gain stages, the signal level at the output of the analogue routing block should not exceed +8.69db, assuming both fi ne and coarse output gain stages are set to a gain of 0db. the sub-audio level is nor mally set to 31mvrms 1.0db, which means that the output from the soft limiter must not exceed 803mvr ms. if pre-emphasis is used, an output signal at 3000hz will have three times the amplitude of a signal at 1000hz, so the signal level before pre-emphasis should not exceed 268mvrms. if the compressor is also used, its ?knee? is at 100mvrms, which would allow a signal into the compressor of 718mvrms, whic h is less than the maximum signal level. the fine
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 36 d/148/6 input gain adjustment has a maximum attenuation of 3.5db and no gain, whereas the coarse input gain adjustment has a variable gain of up to +22.4db and no attenuation. if the highest gain setting were used, then the maximum allowable input signal level at the micfb pin would be 54mvrms. with the lowest gain setting (0db), the maximum allowable input si gnal level at the micfb pin would be 718mvrms. 7.14.2. receive path levels for the maximum signal out of the audio pin, the signal level at the output of the analogue routing block should not exceed +8.69db, assuming both fine and coarse output gain stages are set to a gain of 0db. in this case, there is no sub-audio signal to be added, so the maximum signal level remains at 838mvrms. if de-emphasis is used, an output signal at 300hz will hav e three and a third times the amplitude of a signal at 1000hz, so the signal level before de-emphasis s hould not exceed 251mvrms. if the expander is also used, its ?knee? is at 100mvrms, which would allo w a signal into the expander of 158mvrms. the fine input gain adjustment has a maximum attenuation of 3.5db and no gain, whereas the coarse input gain adjustment has a variable gain of up to +22.4db and no attenuation. if the highest gain setting were used, then the maximum allowable input signal level at the discfb pin would be 12.0mv rms. with the lowest gain setting (0db), the maximum allowable input signal level at the discfb pin would be 158mvrms. the signal level of +8.69db (838mvrms) is an absolute maximum, which should not be exceeded anywhere in the signal processing chain if severe distortion is to be avoided. in-band tones msk/ffsk/audio tones sub-audio processing voice processing mux $b1: b5-2 mux $c1: b15-2 mux $a7: b15-12 $c1: b15-2 mux $b1: b9-6 audio mod1 mod2 disc sig mic input1 input2 output1 output2 fine gain: $cd:110x fine gain: $cd:110x coarse gain: $b0:b14-12 coarse gain: $b0:b10-8 coarse gain: $b0:b3-0 fine gain: p4.2 or $cd:011x offset: p4.4 fine gain: p4.3 or $cd:100x offset: p4.5 tone level: $cd:001x or p1.0 rx voice level: $cd:010x level: p2.0 fine gain: p4.0 fine gain: p4.1 input2 gain: $b1:b15-13 input1 gain: $b1:b12-10 note: rx voice level adjust ($cd:010x) is only active in rx mode tx mult ($cd:101x) is only active in tx mode tx mult x2,x4,x8: $cd:101x figure 19 level adjustments
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 37 d/148/6 8. configuration guide 8.1. c-bus register details addr. (hex) register word size (bits) $01 w c-bus reset 0 $a7 w auxadc and tx mod mode 16 $a8 w auxdac control/data 16 $a9 r auxadc1 data 16 $aa r auxadc2 data 16 $ab w sysclk1 pll data 16 $ac w sysclk1 ref 16 $ad w sysclk2 pll data 16 $ae w sysclk2 ref 16 $af reserved $b0 w analogue output gain 16 $b1 w input gain and output signal routing 16 $b2 reserved $b3 reserved $b4 reserved $b5 w auxadc threshold data 16 $b6 w modem address 16 $b8 reserved $b9 reserved $bb reserved $bc reserved $bd reserved $be reserved $bf reserved $c0 w power-down control 16 $c1 w mode control 16 $c2 w audio control 16 $c3 w tx inband tones 16 $c5 r rx data 1 16 $c6 r status 16 $c7 w modem control 16 $c8 w programming 16 $c9 r rx data 2 16 $ca w tx data 1 16 $cb w tx data 2 16 $cc r tone status/device identification 16 $cd w audio tone 16 $ce w interrupt mask 16 $cf reserved the detailed descriptions of the c-bus registers ar e presented in numerical order and should be read in conjunction with the relevant functional descriptions. all other c-bus addresses (including those not list ed above) are either reserved for future use or allocated for production testing and must not be accessed in normal operation.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 38 d/148/6 8.1.1. reset operations a power-on reset is automatically performed when power is applied to the CMX148. a reset can also be issued as a c-bus command, either as a general re set command ($01), or by setting the appropriate bit (b5) in the powerdown control register ($c0). in the latter case, an option exists to protect the values held in the program block (which is accessed via the programming register, $c8). the action of each reset type is shown in the table below: table 6 reset operations reset type protect bit ($c0 b4) state program block state 1 power-on cleared by h/w default 2 general reset (c-bus $01) cleared by h/w default 3 reset (c-bus $c0 b5) 0 default 4 reset (c-bus $c0 b5) 1 protected 8.1.2. general reset - $01 write the general reset command has no data attached to i t. it sets all operational c-bus registers to $0000, (apart from the registers marked as reserved ). note that some transient data may appear in the following registers during the power-up process ? this should be ignored: status $c6 tone status $cc auxadc1 data $a9 auxadc2 data $aa rx data 1 $c5 rx data 2 $c9 once the prg flag (status register, $c6 bit 0) is set to 1, the device is available for use and the device identification code ($1480) can be read fr om the tone status register ($cc). a power-on reset performs the same action as a general reset command. 8.1.3. interrupt operation the CMX148 will issue an interrupt on the irqn pin when the irq bit (bit 15) of the status register and the irq mask bit (bit 15) are both set to 1. the irq bit is set when the state of any of the interrupt flag bits in the status register changes from 0 to 1 and the co rresponding mask bit(s) in the interrupt mask register is(are) set. enabling an interrupt by setting a mask bit (0 1) after the corresponding status register bit has already been set to 1 will also c ause the irq bit to be set to 1. all interrupt flag bits in the status register, exc ept the program flag (prg, $c6 bit 0), are cleared and the interrupt request is cleared following the command/address phase of a c-bus read of the status register. the prg flag is set to 1 only when it is permissible to write a new word to the programming register. see: o status ? $c6 read o interrupt mask - $ce write 8.1.4. general notes in normal operation, the most significant registers are: o mode control ? $c1 write o status ? $c6 read o analogue output gain - $b0 write o input gain and output signal routing - $b1 write o audio control ? $c2 write setting the mode register to either rx or tx will aut omatically increase the internal clock speed to its operational rate, whilst setting the mode register to idle will automatically return the internal clock to a
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 39 d/148/6 lower (powersaving) rate. to access the program blocks (through the programming register, $c8) the device must be in idle mode. under normal circumstances the CMX148 manages the main clock control automatically, using the default values loaded in program block 3. 8.1.5. auxadc and tx mod mode - $a7 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx mod mode aux adc2 av mode aux adc2 i/p select aux adc1 av mode aux adc1 i/p select 0 0 tx mod mode b15 b14 b13 b12 output1 output2 1 1 1 1 reserved 1 1 1 0 reserved 1 1 0 1 reserved 1 1 0 0 reserved 1 0 1 1 inband inband + sub-audio 1 0 1 0 reserved 1 0 0 1 reserved 1 0 0 0 reserved 0 1 1 1 reserved 0 1 1 0 reserved 0 1 0 1 reserved 0 1 0 0 reserved 0 0 1 1 inband + sub-audio inband + sub-audio 0 0 1 0 inband + sub-audio sub-audio 0 0 0 1 inband sub-audio 0 0 0 0 bias bias to select the routing between the output1, output2 and mod1, mod2 and audio, see section 8.1.12 auxadc av eraging mode b11 b10 auxadc2 b6 b5 auxadc1 1 1 reserved 1 0 reserved 0 1 rolling average, uses program block 3.0 value 0 0 no averaging auxadc input select b9 b8 b7 auxadc2 b4 b3 b2 auxadc1 1 1 1 adc4 1 1 0 adc3 1 0 1 adc2 1 0 0 adc1 0 1 1 mic 0 1 0 sig 0 0 1 disc 0 0 0 off
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 40 d/148/6 8.1.6. auxdac control/data - $a8 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ena 0 0 ram dac dac sel auxdac data/ramdac control b15 enable selected auxdac 0 = disable 1 = enable b14 reserved b13 reserved b12 ramdac enable 0 = auxdac1 operates normally 1 = auxdac1 operates as a ramdac 2 . data in b0-6 controls the ramdac functions. b11-b10 select the auxdac that b9-b0 data will be written to 00 = auxdac1 01 = auxdac2 10 = auxdac3 11 = auxdac4 b9-b0 auxdac data (unsigned) note: the c-bus latency period (250s) should be observed between successive writes to this register. note: when $a8 b12 is set to 1, writing data to this register controls the ramdac settings. writing to auxdac1 whilst the ramdac is still ramping ma y cause unintended operation. in this mode b10 and b11 are ignored and b9 to b0 perform the following functions: b9 reserved , clear to 0 b8 reserved , clear to 0 b7 reserved , clear to 0 b6 ramdac ram access, 0 resets the internal ramdac address pointer ramdac scan time b5 b4 b3 divider time (ms) 0 0 0 1024 10.50 0 0 1 512 5.25 0 1 0 256 2.63 0 1 1 128 1.31 1 0 0 64 0.66 1 0 1 32 0.33 1 1 0 16 0.16 1 1 1 8 0.08 b2 scan direction: 0 = ramp down 1 = ramp up b1 autocycle 0 = disable 1 = continuous ramp up/down b0 ramdac start 0 = stop 1 = start ramdac ramping to initiate a ramdac ramp up write: $9005 to initiate a ramdac ramp down, write: $9001 note that initiating a ramdac scan will automatic ally bring auxdac1 out of powersave. to place auxdac1 back into powersave, it must be written to explicitly. do not change idle/rx/tx mode whilst the ramdac is still ramping. 2 do not write to directly to auxdac 1 whilst the ramdac is in operation. ramdac is only available when in tx mode.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 41 d/148/6 8.1.7. auxadc1 data - $a9 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 threshold status x x x x aux adc 1 data b15-14 threshold status b15 = 1 signal is above the high threshold = 0 signal is below the high threshold b14 = 1 signal is below the low threshold = 0 signal is above the low threshold b13 reserved b12 reserved b11 reserved b10 reserved b9?0 auxadc1 data or last reading (unsigned) 8.1.8. auxadc2 data - $aa read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 threshold status x x x x aux adc 2 data b15-14 threshold status b15 = 1 signal is above the high threshold = 0 signal is below the high threshold b14 = 1 signal is below the low threshold = 0 signal is above the low threshold b13 reserved b12 reserved b11 reserved b10 reserved b9-0 auxadc2 data or last reading (unsigned) 8.1.9. sysclk1 and sysclk2 pll data - $ab, $ad write c-bus address: $ab ? sysclk1 pll c-bus address: $ad ? sysclk2 pll 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vco op divide ratio <5-0> pll feedback divide ratio <9-0> b15-10 divide the selected output clock source by the value in these bits, to generate the system clock output. divide by 64 is selected by setting these bits to 0. b9-0 divide system clock pll vco clock by val ue set in these bits as feedback to the pll phase detector (pd); when the pll is stable, this will be the same frequency as the internal reference as set by b8-b0 of the system clock reference and source configuration register ($ac). divide by 1024 is selected by setting these bits to 0.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 42 d/148/6 8.1.10. sysclk1 and sysclk2 ref - $ac and $ae write c-bus address: $ac ? sysclk1 ref c-bus address: $ae ? sysclk2 ref 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 select and ps clock sources o/p slew ref clock divide ratio <8-0> b15,12,11 clock output divider source sysclk1 source b15 b12 b11 xtal 0 x x sysclk1 pll 1 0 0 main pll 1 0 1 test 1 1 x sysclk2 source b15 b12 b11 xtal 0 x x sysckl2 pll 1 0 0 main pll 1 0 1 sysclk1 pll 1 1 0 test 1 1 1 b14 powersave pll 0 = powersave 1 = enabled b13 powersave output divider 0 = powersave/bypass 1 = enabled b10-9 output slew rate b10 b9 output slew rate 0 0 normal 0 1 slow 1 x fast b8-b0 reference clk divide value. divide by 512 func tion is selected by setting these bits to 0. note that after a general reset, there will be no signal present on the sysclk1 and sysclk2 pins.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 43 d/148/6 8.1.11. analogue output gain - $b0 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 inv_1 mod1 attenuation inv_2 mod2 attenuation ramp up/dn 0 0 0 audio output attenuation this register provides attenuation of the mod1, mod2 and audio output signals, but no gain. likewise, the fine gain adjustment (p4.2-3) only provides signal attenuation. if the signal out put is too small, then the input gain stages (register $b1) will need to be adjusted. b15 mod1 output polarity 0 = true 1 = inverted b11 mod2 output polarity 0 = true 1 = inverted used when interfacing with rf circuitry or when generating an inverted turn-off code for ctcss. any change will take place immediately (w ithin the c-bus latency period) after these bits are changed. b14 b13 b12 mod1 output attenuation b10 b9 b8 mod2 output attenuation 0 0 0 >40db (default) 0 0 1 12db 0 1 0 10db 0 1 1 8db 1 0 0 6db 1 0 1 4db 1 1 0 2db 1 1 1 0db b7 ramp up/down enable 0 = off 1 = on when bit 7 is set to 1 the mod output signal s are ramped to reduce transients in the transmitted signal. the ramp up/down time is se t in the ?ramp rate control? section of the program block (p4.6). bits 6 to 4 are reserved - set to 0. b3 b2 b1 b0 audio output attenuation 0 0 0 0 >60db (default) 0 0 0 1 44.8db 0 0 1 0 41.6db 0 0 1 1 38.4db 0 1 0 0 35.2db 0 1 0 1 32.0db 0 1 1 0 28.8db 0 1 1 1 25.6db 1 0 0 0 22.4db 1 0 0 1 19.2db 1 0 1 0 16.0db 1 0 1 1 12.8db 1 1 0 0 9.6db 1 1 0 1 6.4db 1 1 1 0 3.2db 1 1 1 1 0db note that fine control of output1 and output2 levels can be achieved with the fine output gain 1 and fine output gain 2 registers (p4.2-3). these affect the mod1 , mod2 and audio outputs according to the routing set in registers $a7 and $b1
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 44 d/148/6 8.1.12. input gain and output signal routing - $b1 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 input2 gain input1 gain mod1 source mod2 source audio source input1 routing input2 routing 0 0 b12 b11 b10 input1 gain b15 b14 b13 input2 gain 0 0 0 0db (default) 0 0 1 3.2db b7 mod2 source 0 1 0 6.4db 0 bias -> mod2 (default) 0 1 1 9.6db 1 output2 -> mod2 1 0 0 12.8db 1 0 1 16.0db b6 audio source 1 1 0 19.2db 0 bias -> audio (default) 1 1 1 22.4db 1 output1 -> audio b9 b8 mod1 source 0 0 bias (default) 0 1 bias 1 0 output1 -> mod1 1 1 output2 -> mod1 b5 b4 input1 signal routing b3 b2 input2 signal routing 0 0 bias (default) 0 1 disc 1 0 sig 1 1 mic output1 and output2 signal source s are also defined in section 8.1.5. bits 1, 0 are reserved ? clear to 0. in normal operation, all signal processing blocks would be set to work with input1. there are a number of applications where it may be desirable to split the pr ocessing across both inputs. such applications could be monitoring two rf receivers, or where an exter nal voice encryption unit is required which does not pass sub-audio signalling in rx (in which case, input1 could be routed from the disc input with voice and inband processing set to input2 from the sig input). similarly, for the output routing, under normal operati on, in tx mode, output1 would be routed to mod1 and output2 to mod2. the signals that appear on out put1 and output2 are defined in the tx mod mode register, $a7 bits14-12. if the audio output is selected in tx mode (using b6) it will present the signal that has been routed to output1. this can be used for ?sidetone? when trans mitting inband signalling in 1 or 2-point modulation modes. in rx mode, the audio process is automatically routed to output1. an audio output is only available when in rx or tx mode. 8.1.13. reserved - $b2 write 8.1.14. reserved - $b3 write 8.1.15. reserved - $b4 read
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 45 d/148/6 8.1.16. auxadc threshold data - $b5 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc sel high /low 0 0 0 0 aux adc threshold data b15 auxadc select 0 = auxadc1 1 = reserved b14 high/low select 0 = low threshold 1 = high threshold b13 reserved 0 b12 reserved 0 b11 reserved 0 b10 reserved 0 b9-0 threshold data 8.1.17. modem address - $b6 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msk header address 0 0 0 0 0 0 0 0 b15 ? 8 msk header address b7 ? 0 reserved, clear to 0 8.1.18. reserved - $bb read 8.1.19. powerdown control - $c0 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sig amp mic amp disc amp ip1 ena op1 ena op2 ena mod1 ena mod2 ena audio ena bias reset protect xtal dis ip2 ena 0 0 b15 sig amp enable 0 = off 1 = enabled b14 mic amp enable 0 = off 1 = enabled b13 disc amp enable 0 = off 1 = enabled b12 input1 enable 0 = off 1 = enabled b11 output1 enable 0 = off 1 = enabled b10 output2 enable 0 = off 1 = enabled b9 mod1 enable 0 = off 1 = enabled b8 mod2 enable 0 = off 1 = enabled b7 audio enable 0 = off 1 = enabled b6 bias block enable 0 = off 1 = enabled b5 reset 0 = normal 1 = reset/powersave b4 program block protect 0 = normal 1 = protected if cleared, the program blocks will be initialised on power on or reset. if set, then the program blocks will retain their previous contents. b3 xtal disable 0 = enabled 1 = disabled/powersave setting this bit effectively stops all signal processing within the device. b2 input2 enable 0 = off 1 = enabled b1 reserved 0 1 = do not use b0 reserved 0 1 = do not use note: care should be taken when writing to b5 and b3. these are automatically programmed to an operational state following a power-on (ie: all 0s). writi ng a 1 to either b5 or b3 will effectively cause the device to cease all processing activity, including responding to other c-bus commands (except general reset, $01). when b5 is set, the device will be held in reset and all signal processing will cease (including auxadc operation. when b3 is set the xtal is disabled. when b3 is subsequently cleared, it may take some time for the clock signal to become stable, hence care shoul d be taken in using this feature.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 46 d/148/6 8.1.20. mode control ? $c1 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 audio 0 0 inband modes sub-a udio mode data mode idle/rx/tx b15 reserved 0 b14 audio processing enable 0 = off 1 = enabled (uses input1 source) b13 reserved 0 b12 reserved 0 b11 inband processing source 0 = input1 1 = input2 b10 audio tones enable 0 = off 1 = enabled b9 reserved 0 b8 dtmf enable 0 = off 1 = enabled b7 sub-audio filtering sour ce 0 = input1 1 = input2 b6 ctcss enable 0 = off 1 = enabled b5 dcs enable 0 = off 1 = enabled b4 data processing source 0 = input1 1 = input2 b3 ffsk 2400 enable 0 = off 1 = enabled b2 msk 1200 enable 0 = off 1 = enabled b1-0 operational mode 00 idle 01 rx 10 tx 11 reserved changes to the settings of the bits in this register are implemented as soon as t hey are received over the c-bus (note that the c-bus has a potential latency of up to 250 s). in tx mode, it is not permissible to set both b3 and b2 at the same time. in tx mode, it is only permissible to select one of the following at any time: audio inband signalling msk/ffsk data note that if the audio processing bit (b14) is set at the same time as an in-band signalling bit in tx mode, the in-band signal will be subjected to a 6db gain. if both b5 and b6 are set, then a ?straight-through? path fo r the external sub-audio signal is provided ? this has an essentially flat response from approxim ately 10hz to 2.7khz. in tx mode, input2 should be selected. it is essential that changes to the program blocks and the audio control register are completed before entering rx or tx mode.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 47 d/148/6 the following other registers or bits can be changed as appropriate (note: not all possible changes are appropriate), whilst the device is in tx or rx mode: ? analogue output gain register ($b0) ? auxadc and tx mod mode register ($a7) ? input gain and output signal routing register ($b1) ? power down control register ($c0) ? tx inband tones register ($c3) ? modem control register ($c7) bit 9 only, as described in section 8.1.24 ? tx data registers ($ca and $cb) ? audio tone register ($cd) ? interrupt mask register ($ce) in rx mode, as certain ffsk bit patterns can mi mic inband tones, the inband receiver is temporarily disabled when an ffsk frame sync is detected. if us ing sized packets (formats 1, 4 and 5) the CMX148 will automatically restore inband tone detection when the received message has ended. if using unsized packets (formats 0, 2 and 3) the host must m onitor the received data and restore inband tones (by setting bits 15, 11, 10, 9 and 8, as requir ed) when it has detected the end of data. 8.1.21. audio control ? $c2 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 scra- mble comp emph 12k5 25k hpf 0 0 0 0 0 0 0 0 0 0 b15 audio scrambling enable 0 = off 1 = enabled b14 audio compandor enable 0 = off 1 = enabled b13 audio pre/de-emphasis 0 = off 1 = enabled 3 b12 audio 12.5khz filter enable 0 = off 1 = enabled b11 audio 25khz filter enable 0 = off 1 = enabled b10 audio 300hz hpf enable 0 = off 1 = enabled b9-0 reserved 8.1.22. tx inband tones - $c3 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 twist sgl tx dtmf tone b15-6 reserved , clear to 0. b5 dtmf twist 0 = normal 1 = -2db of twist applied to the lower dtmf tone. b4 dtmf single tone 0 = normal 1 = single tone, see table 2 dtmf tone pairs b3-0 dtmf tone value ? see table 2 dtmf tone pairs see section 7.8.1 and 8.1.26. 3 in order to pre-emphasise the msk/ffsk dat a, program block p1.0 bit 11 should be set.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 48 d/148/6 8.1.23. status ? $c6 read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irq res res dtmf res res aux adc2 aux adc1 data end data rdy data crc 2k4 1k2 res res prg b15 irq changes in the status register will cause this bit to be set to 1 if the corresponding interrupt mask bit is enabled. an interrupt request is iss ued on the irqn pin when this bit is 1 and the irq mask bit (b15 of interrupt mask register, $ce) is set to 1. b14 reserved b13 reserved b12 dtmf event a valid dtmf tone has been detected and can be r ead from the tone status register, $cc. b11 reserved b10 reserved b9 auxadc2 threshold change auxadc2 signal has just gone above the high th reshold or has just gone below the low threshold. the auxadc2 data register $aa should be read to determine the exact cause. b8 auxadc1 threshold change auxadc1 signal has just gone above the high th reshold or has just gone below the low threshold the auxadc1 data register $a9 should be read to determine the exact cause. b7 data end rx mode: this is only valid when bit 6 ?data ready? is set. it is set when receiving the last part of a sized msk/ffsk frame or frame format 1 (frame head only) message, bit 5 (crc) will also be updated at this time. when the host detec ts bit 7 is set it may power down the CMX148 or set the CMX148 to transmit or re ceive new information as appropriate. tx mode: this will be set when the last bit of msk/ffsk data has been transmitted. note; when using formats 0, 2 or 3 (see section 7.9) this bit will only be set if bit 9 of the modem control register ($c7) is set at the appropriate time. a fter allowing a short time delay associated with the external components and radio circuitr y, the host may power down the CMX148 and transmitter or set the CMX148 to transmit or receive new information as appropriate. b6 data ready tx mode: indicates that new transmit data is required. rx mode: received data is ready to be read. for continuous transmission or reception of in formation, a data transfer should be completed within the time appropriate for that data (see table 5). b5 data crc received bit 5 will be set after receiving an incorrect crc portion of a sized data block (frame formats 4 and 5). b4 2400 fsk data received b3 1200 msk data received bits 4 and 3 indicate the received data rate after a valid data sequence has been received. if frame format 0 is enabled these bits will be set on detection of a valid frame sync pattern (the sync data is available in the rx data register). if frame format 0 is disabled then these bits will only be set when a frame head is detected with a correct crc. b2 reserved b1 reserved b0 prg flag when set to 1, this bit indicates that the progra mming register, $c8, is available for the host to write to it. cleared by writing to the programming register, $c8. bits 2 to 15 of the status register are cleared to 0 after the status register is read. the data in this register is not valid if bit 5 of the power down control register, $c0 is set to 1.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 49 d/148/6 8.1.24. modem control - $c7 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sync synd synt 0 0 en_ raw last tx data inter- leave msk/ffsk message format 0 0 user bit scramble seed this register configures the way the CMX148 handles msk data in tx and rx modes. b15 sync detect (msk/ffsk) 0 = off 1 = enabled b14 synd detect (msk/ffsk) 0 = off 1 = enabled b13 synt detect (msk/ffsk) 0 = off 1 = enabled note: sync, synd and synt patterns are defined in program block p0.0-3 b12 reserved 0 b11 reserved 0 b10 en_raw: 0 = data packetising on 1 = raw data mode this selects the raw or formatted mode for type 0 msk/ffsk or dsc data. msk/ffsk receive mode: b10 = 1: device will look for the programmed frame sync. pattern, raise an interrupt (if enabled) and decode the following data 16 bits at a ti me, making them available in rx data 1 register ($c5). b10 = 0: device will look for a complete frame head before raising an interrupt (if enabled) and then decode the following data in accordance with the received message format. the frame head control field bytes, user data and any crc will be presented in the appropriate rx data registers ($c5 and $c9). msk/ffsk transmit mode: b10 = 1: device will transmit data 16 bits at a time from tx data 1 register ($ca). bit and frame sync pattern generation and all formatting of the data have to be performed by the host in this case. b10 = 0: device will transmit the programmed bit and frame sync patterns followed by a frame head containing the information supplied in bits 7?0 of this register and the 2 bytes in tx data 1 register ($ca). subsequently the host must supply data when requested to complete the transmission of the frame head and data block. b9 last tx data: this is only valid when transmitting data with formats 0, 2 or 3 in msk/ffsk modes and indicates to the CMX148 that it can cease m odulation. the host must set this bit to 1 immediately after the interrupt for ?load more data? occurs ($c6 bit 6). in receive, or when transmitting other message formats, this bit must be cleared to 0. b8 interleave: 0 = off 1 = on this bit selects if frame headers in msk/ffsk modes will be interleaved or not. b7-5 data format: b7 b6 b5 format message format 0 0 0 0 raw data (en_raw = 1) 0 0 1 1 frame head only, no payload 0 1 0 2 frame head + unsized payload of raw 16 bit words 0 1 1 3 frame head + unsized payload with fec 1 0 0 4 frame head + sized payload with fec + crc 1 0 1 5 frame head + sized payload with fec + crc + interleaving all other patterns - reserved b4 reserved , clear to 0. b3 reserved , clear to 0. b2 user bit. may be freely used by the host in msk/ffsk m odes. this bit has no effect on the message format or encoding and will be reported in the rx da ta 1 register for the receiving host to use as appropriate. this bit could be used to indi cate a special message, e.g. one containing handset or channel set-up information.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 50 d/148/6 b1-0 scrambler seed select. used when transmitting user-data in msk/ ffsk modes. the receiving CMX148 will automatically de-scramble the re ceived data block using the setting indicated in the received frame head. the receiving host can read the scrambler setting (0-3) used by the transmitter via rx data 1 register ($c5: bits 1,0) and ma y use this when returning messages. see also section 7.9.7. b1 b0 msk data scrambling setting 0 0 standard scrambling (seed = $ffff) 0 1 scramble seed1 (see p0.4-5) 1 0 scramble seed2 (see p0.6-7) 1 1 no scrambling (seed = $0000) 8.1.25. programming register ? $c8 write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 program block address program block data see section 8.2 for a definition of program block operation. 8.1.26. rx data 1 and 2 - $c5 and $c9 read bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $c5 rx data byte 0 (frame head: address byte) rx data byte 1 (frame head: format byte) $c9 rx data byte 2* (frame head: size/user byte) rx data byte 3* (frame head: crc byte) *$c9 is used when receiving format 4 or 5 and frame heads, t he rx buffer is effectively 4 bytes long in these cases. these 2 words hold the most recent 2 bytes (byte 0 and 1) or 4 bytes (b ytes 0, 1, 2 and 3) of msk data decoded. received data is continuous, if the data is not read before the next data is received the current data will be over-written. after receiving a frame head the host can read the address and format bytes for the following packet from rx data 1 register ($c5) and the size/user byte and the frame head checksum a byte from rx data 2 register ($c9). the format byte corresponds to the settings of b0-7 of the modem control register ($c7) used by the transmitting device. the cm x148 will read the size and message formatting information and if the message is of format 3, 4 or 5 (see section 7.9) it will start the automatic decoding of the following data; descrambling, de-interleavi ng, decoding error correction bytes, stripping out pad bytes, calculating and checking checksum b as requi red. the only task the host need perform during the reception of formatted frames is to read out data when it is ready.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 51 d/148/6 8.1.27. tx data 1 and 2 - $ca and $cb write bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $ca tx data byte 0 (frame head: address byte) tx data byte 1 (frame head: size/user byte) $cb tx data byte 2* tx data byte 3* *register $cb is only used for format 4 or 5, the tx buffer is effectively 4 bytes long in these cases. these 2 words hold next 2 bytes (byte 0 and 1) or 4 by tes (bytes 0, 1, 2 and 3) of msk/ffsk data to be transmitted. outgoing data is continuous, if new dat a is not provided before the current data has been transmitted the current data will be re -transmitted, until new data is prov ided. transmission of current data will be completed before transmission of newly loaded data begins. see section 7.8.2. when transmitting formatted msk/ffsk data packets, t he host must first load the correct address and size/user bytes for the following packet into txdata 1 register ($ca). the CMX148 will automatically add the control byte, based on the settings in modem cont rol register ($c7), and calculate the frame head checksum a byte. the CMX148 will read the size and message formatting information and automatically format all following data; adding error correction by tes, adding pad bytes, interleaving, scrambling and calculating and appending checksum b as required. the only task the host need perform during the transmission of a frame is to download new data when it is required. note: these 2 words must be written separat ely, i.e. two 16-bi t c-bus transactions. 8.1.28. tone status - $cc read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device identification code x dtmf tone detected dt x x x x x x x x x x after power-on or general reset, this register will contain the device identif ication code ($1480) related to this particular device. the host c may use this to confirm that t he device is in its correct operational mode before attempting to actively use the device. in normal operation, this word holds the current st atus of the CMX148 inband t one sections. this word should be read by the host after an interrupt caused by an inband tone event. in tx mode this register will be cleared to 0. b15 reserved ? ignore this bit. b10 set if b14-11 represent dtmf tone. b14-11 detected inband frequency; identifie s the frequency by its position in table 2 dtmf tone pairs. a change in the state of bits 14 to 10 will cause bit 12 of the status register ($c6), to be set to 1. b9-0 reserved ? ignore these bits.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 52 d/148/6 8.1.29. audio tone - $cd: write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 audio tone frequency 0 0 1 0 audio tone level 0 1 0 0 rx voice level 0 1 1 0 output1 fine gain (also see p4.2) 1 0 0 0 output2 fine gain (also see p4.3) 1 0 1 0 tx voice level multiplier 1 0 1 1 reserved 1 1 0 0 mod1 and mod2 fine attenuation 1 1 0 1 sub audio tx level 1 1 1 0 reserved 1 1 1 1 reserved all other values reserved bits 15-12 determine how the remaining bit fields will be interpreted: 0000 2 : when the appropriate bits of the mode control register ($c1, b10) are set, an audio tone will be generated with the frequency set by bits (11-0) of this register in acco rdance with the formula below. if bits 11-0 are programmed with 0, no tone (i.e. v bias ) will be generated when the audio tone is enabled. frequency = audio tone (i.e. 1hz per lsb) the audio tone frequency should only be set to generate frequencies from 300hz to 3000hz. the host should disable other audio band signalling and set the correct audio routing before generating an audio tone and re-enable signalling and audio routing on completion of the audio tone. the timing of intervals between these actions is controlled by the host c. this register may be written to whilst the audio tone is being generated, any change in frequency will take place after the end of the c-bus write to this register . this allows complex s equences (e.g. ring or alert tunes) to be generated for the local speaker (tx or rx via the audio pin) or transmitted signal (tx via the mod1/mod2 pins). 0010 2 : the audio tone level may be attenuated by the value wri tten to b11-0. the value of $fff is equivalent to x1 ie: 0db (use with care as high values may result in signal ?clipping?). note that this adjustment will affect all signals generated by the in-band signalli ng block (dtmf, msk/ffsk, audio tone). this register operates in parallel with p1.0, so that the la st register written ($cd with value $2xxx or $c8 p1.0 with value $dxxx) will set the attenuation. with the audio tone ($cd) register, however, the level can be adjusted ?on-the-fly?, thus avoiding the need to drop ba ck into idle mode. approx imate values for 0.2db attenuation steps are shown in . 0100 2 : in rx mode, the voice level may be attenuated by t he value written to b11-0. the value of $fff is equivalent to x1. note that this adjustment will onl y affect signals in the voice processing path as enabled by the mode control register ($c1, b14). this allows the voice level to be adjusted ?on-the-fly?, without needing to drop back into idle mode, and offers a ?f ine gain? volume control when used in conjunction with the coarse gain control (b3-0) of the audio output gain register ($b0). approximate values for 0.2db steps are shown in table 7.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 53 d/148/6 b11-0 value (hex) attenuation (db) b11-0 value (hex) attenuation (db) fff 0 d50 1.6 f90 0.2 cf0 1.8 f40 0.4 cb0 2.0 ee0 0.6 c60 2.2 ea0 0.8 c20 2.4 e50 1.0 bf0 2.6 de0 1.2 ba0 2.8 da0 1.4 b60 3.0 table 7 audio tone register - attenuation steps 0110 2 : the output1 level may be attenuated by the value writt en to b11-0. the value of $fff is equivalent to x1. this register operates in parallel with p4.2 and allo ws the level to be adjusted ?on-the-fly?, without needing to drop back into idle mode. approximate val ues for 0.2db attenuation steps are shown in table 7. 1000 2 : the output2 level may be attenuated by the value writt en to b11-0. the value of $fff is equivalent to x1. this register operates in parallel with p4.3 and allo ws the level to be adjusted ?on-the-fly?, without needing to drop back into idle mode. approximate val ues for 0.2db attenuation steps are shown in table 7. 1010 2 : this sets the value of the tx voice level multiplier at the output of the tx limiter stage. this can be useful in situations where it has been necessary to use a small limiting threshold and still maintain an acceptable level at the mod outputs. the default state is x1. bits 11 - 3 should be set to 0. b2 b1 b0 tx voice level multiplier 0 0 0 x1 0 0 1 x2 0 1 0 x4 0 1 1 x8 1 0 0 x16 1 0 1 x32 1100 2 : mod1 and mod2 fine attenuation controls. these bits attenuate mod1 and mod2 signals in 0.2db steps, as shown below, and may be changed whilst the devic e is in tx or rx mode. bits 11 - 8 should be set to 0. these controls operate in conjunction with the coarse gain controls of the analogue output gain register ($b0). additional gain and offset control of output1 and output2 si gnals, which precedes the mod1 and mod2 fine gain controls, is provided by the settings in register $cd:0110 and $cd:1000. these additional gain and offset controls operate in para llel with the program block registers p4.2 ? 4.5. b3 b2 b1 b0 mod1 fine output attenuation b7 b6 b5 b4 mod2 fine output attenuation 0 0 0 0 0db 0 0 0 1 0.2db 0 0 1 0 0.4db 0 0 1 1 0.6db 0 1 0 0 0.8db 0 1 0 1 1.0db 0 1 1 0 1.2db 0 1 1 1 1.4db
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 54 d/148/6 b3 b2 b1 b0 mod1 fine output attenuation b7 b6 b5 b4 mod2 fine output attenuation 1 0 0 0 1.6db 1 0 0 1 1.8db 1101 2 : the sub audio tx level may be attenuated by the value written to b11-0. the value of $fff is equivalent to x1. this register operates in parallel with p2.0 and allows the level to be adjusted ?on-the-fly?, without needing to drop back into idle mode. approximate va lues for 0.2db attenuation steps are shown in table 7. 8.1.30. interrupt mask - $ce write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 irq 0 0 dtmf 0 0 aux adc2 aux adc1 data end data rdy data crc 2k4 1k2 0 0 prg bit value function 15 1 enable selected interrupts 0 disable all interrupts (irqn pin not activated) 14 0 reserved 13 0 reserved 12 1 enable interrupt when a valid dtmf tone is detected 0 disabled 11 0 reserved 10 0 reserved 9 1 0 enable interrupt when the aux adc 2 status bit changes disabled 8 1 enable interrupt when the aux adc 1 status bit changes 0 disabled 7 1 enable interrupt when msk/ffsk data transmission has ended 0 disabled 6 1 enable interrupt when an msk/ffsk data transfer is required 0 disabled 5 1 enable interrupt when an incorrect crc portion of a sized data block is received 0 disabled 4 1 enable interrupt when valid 2400baud data is detected 0 disabled 3 1 enable interrupt when valid 1200baud data is detected 0 disabled 2 1 reserved 1 1 reserved 0 1 enable interrupt when prg flag bit of t he status register changes from 0 to 1 (see programming register $c8) 0 disabled 8.1.31. reserved - $cf write this c-bus address is allocated for production test ing and must not be accessed in normal operation.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 55 d/148/6 8.2. programming register operation in order to support radio systems that may not comply with the default settings of the CMX148, a set of program blocks is available to customise the features of the device. it is env isaged that these blocks will only be written to following a power-on of the devic e and hence can only be accessed while the device is in idle mode. access to these blocks is via the programming register ($c8). all other interrupt sources should be disabled and t he auxadcs switched off while loading the program blocks. the programming register should only be written to when t he prg flag ($c8 bit 0) of the status register is set to 1, the rx and tx modes are disabled (bits 0 and 1 of the mode control register both 0) and the auxadc is disabled. the prg flag is cleared when the programming regi ster is written to by the host. when the corresponding programming action has been completed ( normally within 250s) the CMX148 will set the flag back to 1 to indicate that it is now safe to wr ite the next value. the progr amming register must not be written to while the prg flag bit is 0. programming is performed by writing a sequence of 16-bit words to the programming register in the order shown in t he following tables. writing data to the programming register must be performed in the order shown for each of the program blocks, however the order in which the blocks are written is not critical. if later words in a block do not require updating, the user may stop programming that block when the last change has been performed. e.g. if only 'fine output gain 1' needs to be changed the host will need to write to program block p4.0, p4.1 and p4.2 only. the user must not exceed the def ined word counts for each block. the internal pointer for each program block write is initialised by setting b15 to 1. b14-12 are then used to select the particular program block in use as shown in table 8. subsequent writes to the programming register (with b15 cleared to 0) will increment the poi nter until the end of the program block is reached. program block 3 has an additional feature to facilit ate ramdac programming, where the first eleven entries of the block may be skipped by setting both b15 and b10 to 1 to initialise the pointer directly to the start of the ramdac table. table 8 program block selection b15 b14 b13 b12 bit field (max) 1 0 x x select block 4 14 1 1 0 0 select block 0 12 1 1 0 1 select block 1 12 1 1 1 0 select block 2 12 1 1 1 1 select block 3 12 once the final write to the programming register has been executed, a final check of the prg flag should be performed before returning to normal operation.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 56 d/148/6 8.2.1. program block 0 ? modem configuration bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.0 1 1 0 0 pre 0 msk/ffsk frame sync lsb p0.1 0 1 0 0 0 msk/ffsk frame sync msb p0.2 0 1 0 0 0 msk/ffsk frame synd lsb p0.3 0 1 0 0 0 msk/ffsk frame synd msb p0.4 0 1 0 0 0 scramble seed 1 lsb p0.5 0 1 0 0 0 scramble seed 1 msb p0.6 0 1 0 0 0 scramble seed 2 lsb p0.7 0 1 0 0 0 scramble seed 2 msb p0.8 0 1 0 0 0 msk/ffsk bit sync lsb p0.9 0 1 0 0 0 msk/ffsk bit sync msb default values: p0.0 $c023 p0.5 $4000 p0.1 $40cb p0.6 $4000 p0.2 $4033 p0.7 $4000 p0.3 $40b4 p0.8 $4055 p0.4 $4000 p0.9 $4055 this initiates the device with the msk frame sync pa ttern of $cb23 and bit sync of alternate 1s and 0s. $c8 (p0.0-3) msk frame sync bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.0 1 1 0 0 pre 0 msk/ffsk frame sync lsb p0.1 0 1 0 0 0 msk/ffsk frame sync msb p0.2 0 1 0 0 0 msk/ffsk frame synd lsb p0.3 0 1 0 0 0 msk/ffsk frame synd msb bits 7 to 0 set the frame sync pattern used in tx and rx msk data. bit 7 of the msb is compared to the earliest received data. note that synt is the inverse pattern of sync. bit 11 of p0.0 enables pre-emphasis of the transmitted msk/ffsk/fsk signal (default = 0, disabled). $c8 (p0.4-7) scramble seed 1 and 2 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.4 0 1 0 0 0 scramble seed 1 lsb p0.5 0 1 0 0 0 scramble seed 1 msb p0.6 0 1 0 0 0 scramble seed 2 lsb p0.7 0 1 0 0 0 scramble seed 2 msb these bits set the scramble seed used on all data bits following a frame head. if $0000 is programmed as the seed then no scrambling will occur when sele cted. if either programmable scramble seeds are selected, both the transmit and receiv e devices must use the same seed pattern for data to be transferred correctly. $c8 (p0.8-9) msk bit sync bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p0.8 0 1 0 0 0 msk/ffsk bit sync lsb p0.9 0 1 0 0 0 msk/ffsk bit sync msb this bit pattern is used when transmitting the bit sync portion of a frame head.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 57 d/148/6 8.2.2. program block 1 ? inband tone setup bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1.0 1 1 0 1 audio band tones/data tx level emph default value: p1.0: $d800 $c8 (p1.0) audio band tones tx level bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p1.0 1 1 0 1 audio band tones/data tx level emph bits 11 (msb) to 1 (lsb) set the transmitted i nband tone, audio tone and msk/ffsk signal level (p-p) with a resolution of av dd /2048 per lsb (1.611mv per lsb at av dd =3.3v). valid range for this value is 0 to 1536 ? use with care as higher val ues may result in signal ?clipping?. bit 0 controls inband tone de-emphasis. when inband t ones are enabled in the mode control register ($c1), de/pre-emphasis is enabled in the audio control register ($c2) and this bit (b0) is set to 1; signals going to the inband tone detector are de-emphasised in accordance with figure 9 of the datasheet. this combination of settings should only be used in rx mode. if this bit is set, then in tx mode, the user is advised to clear the de/pre-emphasis bit in the audio c ontrol register ($c2). this has no effect on dtmf signals.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 58 d/148/6 8.2.3. program block 2 ? ctcss and dcs setup bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2.0 1 1 1 0 ctcss and dcs tx level p2.1 0 1 1 0 reserved - 0 p2.2 0 1 1 0 reserved - 0 p2.3 0 1 1 0 reserved - 0 p2.4 0 1 1 0 reserved - 0 p2.5 0 1 1 0 0 0 0 0 0 0 0 0 0 0 hpf p2.6 0 1 1 0 reserved - 0 default values: p2.0 $e800 p2.3 $6000 p2.1 $6000 p2.4 $6000 p2.2 $6000 p2.5 $6000 p2.6 $6000 $c8 (p2.0) ctcss and dcs tx level bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2.0 1 1 1 0 ctcss and dcs level bits 11 (msb) to 0 (lsb) set the transmitted external ctcss or dcs sub-audio signal level (p-p) with a resolution of av dd /16384 per lsb (0.201mv per lsb at av dd =3.3v, giving a range 0 to 824.8mv p-p) 4 . $c8 (p2.1 to 2.4) reserved $c8 (p2.5) 300hz high-pass filter select bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2.5 0 1 1 0 0 0 0 0 0 0 0 0 0 0 hpf select the hpf select field determines the cut-o ff point of the 300hz audio high-pass filter: 00 = 300hz (default) 01 = 280hz 10 = 320hz 11 = reserved $c8 (p2.6) reserved ? do not access bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p2.6 0 1 1 0 reserved ? set to $000 4 assuming a 1648mv pk-pk input signal with input and output gains set for 0db.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 59 d/148/6 8.2.4. program block 3 ? auxdac, ramdac and clock control this block is divided into two sections to facilitate loading the ramdac buffer. set bit 15 to 1 and clear bit 10 to 0 to start the loading sequence from p3.0. set both bits 15 and 10 to start the loading sequence from p3.11 (ramdac data). the internal clk dividers only require modifi cation if a non-standard xtal frequency is used (see table 1 ) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p3.0 1 1 1 1 0 0 0 0 auxadc1 average counter p3.1 0 1 1 1 0 0 0 0 reserved p3.2 0 1 1 1 gp timer value in idle mode p3.3 0 1 1 1 vco output and aux clk divide in idle mode p3.4 0 1 1 1 ref clk divide in rx or tx mode p3.5 0 1 1 1 pll clk divide in rx or tx mode p3.6 0 1 1 1 vco output and aux clk divide in rx or tx mode p3.7 0 1 1 1 0 0 0 0 internal adc / dac clk divide in rx or tx mode p3.8 0 1 1 1 0 0 0 0 adc internal control 1 p3.9 0 1 1 1 0 0 0 0 adc internal control 2 p3.10 0 1 1 1 0 0 0 0 0 0 0 0 adc internal control 3 p3.11 1 1 1 1 0 1 user defined ramdac data 0 p3.xx 0 1 1 1 0 1 user defined ramdac data xx p3.74 0 1 1 1 0 1 user defined ramdac data 63 default values: p3.0 $f000 p3.1 $7000 p3.2 - p3.7: see table 1 p3.8 $7000 p3.9 $7101 p3.10 $7002 p3.11 - p3.74: see table 9 table 9 ramdac values default ramdac contents after reset (hex) 0 000 1 001 2 003 3 006 4 00a 5 010 6 017 7 01f 8 028 9 033 10 03e 11 04b 12 059 13 068 14 078 15 089 16 09a 17 0ad 18 0c1 19 0d5 20 0ea 21 100 22 116 23 12d 24 145 25 15d 26 175 27 18e 28 1a7 29 1c0 30 1d9 31 1f3 32 20c 33 226 34 23f 35 258 36 271 37 28a 38 2a2 39 2ba 40 2d2 41 2e9 42 2ff 43 315 44 32a 45 33e 46 352 47 365 48 376 49 387 50 397 51 3a6 52 3b4 53 3c1 54 3cc 55 3d7 56 3e0 57 3e8 58 3ef 59 3f5 60 3f9 61 3fc 62 3fe 63 3ff
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 60 d/148/6 8.2.5. program block 4 ? gain and offset setup bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.0 1 0 fine input gain 1 p4.1 0 0 fine input gain 2 p4.2 0 0 fine output gain 1 p4.3 0 0 fine output gain 2 p4.4 0 0 output1 offset control p4.5 0 0 output2 offset control p4.6 0 0 ramp rate control p4.7 0 0 limiter setting p4.8 0 0 scrambler inversion frequency p4.9 0 0 audio filter sequence p4.10 0 0 reserved p4.11 0 0 inputagc threshold level default values: p4.0 $8000 p4.6 $0000 p4.1 $0000 p4.7 $3fff p4.2 $0000 p4.8 $119a p4.3 $0000 p4.9 $001b p4.4 $0000 p4.10 $0608 p4.5 $0000 p4.11 $0fff $c8 (p4.0) fine input gain 1 and fine input gain 2 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.0 1 0 fine input gain 1 (unsigned integer) p4.1 0 0 fine input gain 2 (unsigned integer) gain = 20 log([32768-ig]/32768)db. ig is the unsigned int eger value in the ?fine input gain? field. fine input gain adjustment should be kept within the r ange 0 to -3.5db. this adjustment occurs after the coarse input gain adjustment (register $b1). $c8 (p4.2-3) fine output gain 1 and fine output gain 2 bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.2 0 0 fine output gain 1 (unsigned integer) p4.3 0 0 fine output gain 2 (unsigned integer) gain = 20 log([32768-og]/32768)db. og is the unsigned integer value in the ?fine output gain? field. fine output gain adjustment should be kept within t he range 0db to -3.5db. this adjustment occurs before the coarse output gain adjustment (register $b0). alteration of fine output gain 1 will affect the gain of both mod1 and audio outputs. $c8 (p4.4-5) output1 offset and output2 offset bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.4 0 0 2?s complement offs et for mod1, resolution = av dd / 65536 per lsb p4.5 0 0 2?s complement offset for mod2, resolution = av dd / 65536 per lsb
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 61 d/148/6 the programmed value is subtracted from the out put signal. can be used to compensate for inherent offsets in the output path via mod1 (output1 offset ) and mod2 (output2 offset). it is recommended that the offset correction is kept within the range +/-50mv. this adjustment occurs before the coarse output gain adjustment (register $b0), therefore an alteration to the latter register will require a compensation to be made to the output offsets. $c8 (p4.6) ramp rate control bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.6 0 0 ramp rate up control ( rru) ramp rate down control (rrd) the ramp-up and ramp-down rates can be independently programmed. the ramp rates apply to all the analogue output ports. they only affect those ports bei ng turned on (ramp-up) or turned off (ramp down). the ramp rates should be programmed before ramping any outputs. time to ramp-up to full gain = (1 + rru) 1.333ms time to ramp down to zero gain = (1 + rrd) 1.333ms ramp up starts from when the transmit mode starts (mode control register bit 1 set = 1). ramp down starts from when transmit mode is turned o ff (mode control register bit 1 cleared = 0). $c8 (p4.7) transmit limiter control bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.7 0 0 limiter setting this unsigned number sets the clipping point (maximum deviation from the centre value) for the mod1 and mod2 pins. the maximum setting ($3fff) is v bias (av dd /2) i.e. output limited from 0 to av dd . for an av dd of 3.3v, the resolution is approx. 0.3mv per lsb. limiter threshold v p4.7 0 500 1000 1500 2000 2500 0 1000 2000 3000 4000 5000 6000 7000 8000 p4.7 value (decimal) pk-pk output level (mv) limit figure 20 limiter values the limiter is set to maximum following a c-bus rese t or a power-up reset. the levels of internally generated signals may need to be adjusted by setting appropr iate transmit levels to avoid un-intentional limiting.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 62 d/148/6 $c8 (p4.8) scrambler inversion frequency bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.8 0 0 scrambler inversion frequency = f / 0.7324 this unsigned hex number sets the inversion fr equency for the voice scrambler and de-scrambler (default is 3300hz). $c8 (p4.9) audio filter sequence bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.9 0 0 limit src inputagc pre-emp comp scramble 300hz b13 sets the position of the limiter in the audio proc essing chain. the default is a soft limiter function; setting this bit provides a hard limiter function. b12 sets the source of the reference si gnal when the inputagc function is active. 0 = audio input 1 = pre-emphasis output b11-8 control the hardware inputagc function and its re lease timer for voice/audio signals on input1 in 64ms steps: 0000 inputagc off 0001 inputagc on, release time = 64ms 0010 inputagc on, release time = 128ms 0011 inputagc on, release time = 196ms 0100 inputagc on, release time = 256ms 0101 inputagc on, release time = 320ms - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1111 inputagc on, release time = 960ms b7-0 set the order of the audio filter processing. th is feature can be used to optimise the signal to noise performance of particular radio hardware designs. each filter/process block can be specified in any order. each two-bit field specifies the order in which the process will be executed in tx mode, therefore it is imperative that each set of bit fields be different. the reverse sequence is used in rx mode. the voice filter and soft limiter will always be implement ed as the final block in the tx sequence. the default settings are: o pre-emp: 00 o compress: 01 o scramble: 10 o 300hz hpf: 11 which will implement the line-up as shown in figure 21 and figure 22. pre-emph (optional) compress (optional) scrambler (optional) voice lpf & soft limiter 300hz filter audio in + ctcss figure 21 default tx audio filter line-up discrim 300hz filter de-scrambler (optional) expandor (optional) de-emph (optional) audio voice lpf figure 22 default rx audio filter line-up
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 63 d/148/6 an alternative, preferred, line-up is shown in figure 23 and figure 24 for the following settings (p4.9 = $004b): o pre-emp: 01 o compress: 00 o scramble: 10 o 300hz hpf: 11 compress (optional) pre-emph (optional) scrambler (optional) voice lpf & soft limiter 300hz filter audio in + ctcss figure 23 preferred tx audio filter line-up discrim de-emph (optional) 300hz filter de-scrambler (optional) expander (optional) audio voice lpf figure 24 preferred rx audio filter line-up $c8 (p4.10) reserved bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.10 0 0 reserved ? set to $0608 reserved ? set to $0608 $c8 (p4.11) inputagc threshold level bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p4.11 0 0 threshold setting, resolution = av dd /16384 per lsb this unsigned number sets the threshold point (maximum deviation from the centre value) for the input agc function, where the input gain will be stepped to avoid exceeding the specification limits. the threshold is set to half of full-scale ($0fff = v bias (av dd /4)) following a c-bus reset or a power- up reset. 8.2.6. initialisation of the program blocks removal of the signal processing block from reset (power-down register, $c0, b5 1 0), with b4 kept low (= 0), will cause all of the program blocks (p0 ? p4) to be reset to their default values.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 64 d/148/6 9. performance specification 9.1. electrical performance 9.1.1. absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply: dv dd - dv ss ? 0.3 4.5 v av dd - av ss ? 0.3 4.5 v voltage on any pin to dv ss ? 0.3 dv dd + 0.3 v voltage on any pin to av ss ? 0.3 av dd + 0.3 v current into or out of any power supply pin (excluding v bias ) (i.e. v dec , av dd , av ss , dv dd , dv ss) ? 30 +30 ma current into or out of any other pin ? 20 +20 ma voltage differential between power supplies: dv dd and av dd 0 0.3 v dv ss and av ss 0 50 mv q3 package (48-pin vqfn) min. max. unit total allowable power dissipation at tamb = 25c ? 1750 mw ... derating ? 17.5 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c l4 package (48-pin lqfp) min. max. unit total allowable power dissipation at tamb = 25c ? 1600 mw ... derating ? 16 mw/c storage temperature ? 55 +125 c operating temperature ? 40 +85 c 9.1.2. operating limits correct operation of the device outsi de these limits is not implied. notes min. max. unit supply voltage: dv dd ? dv ss 3.0 3.6 v av dd ? av ss 3.0 3.6 v v dec ? dv ss 12 2.25 2.75 v operating temperature ? 40 +85 c xtal/clk frequency (using a xtal) 11 3.0 12.288 mhz xtal/clk frequency (using an external clock) 11 3.0 24.576 mhz notes: 11 nominal xtal/clk frequency is 3.6864mhz. 12 the v dec supply is automatically created from dv dd by the on-chip voltage regulator.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 65 d/148/6 9.1.3. operating characteristics for the following conditions unless otherwise specified: external components as recommended in figure 2. maximum load on digital outputs = 30pf. xtal frequency = 3.6864mhz 0.01% (100ppm); tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v reference signal level = 308mv rms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db. output stage gain = 0db. dc parameters notes min. typ. max. unit supply current 21 all powersaved di dd (dv dd = 3.3v, v dec = 2.5v) ? 8 100 a ai dd (av dd = 3.3v) ? 4 20 a idle mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) ? 1.12 ? ma ai dd (av dd = 3.3v) ? 250 ? a rx mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) ? 6.80 ? ma ai dd (av dd = 3.3v) ? 3.05 ? ma tx mode 22 di dd (dv dd = 3.3v, v dec = 2.5v) ? 6.33 ? ma ai dd (av dd = 3.3v) ? 6.90 ? ma additional current for auxiliary adc di dd (dv dd = 3.3v, v dec = 2.5v) ? 50 ? a additional current for each auxiliary dac ai dd (av dd = 3.3v) ? 200 ? a notes: 21 tamb = 25c. not including any current dr awn from the device pins by external circuitry. 22 auxiliary circuits, audio scrambler , compandor and pre/de-emphasis disabled, but all other digital circuits (including the main clock pll) enabled. a single analogue path is enabled through the device.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 66 d/148/6 dc parameters (continued) notes min. typ. max. unit xtal/clk 25 input logic 1 70% ? ? dv dd input logic 0 ? ? 30% dv dd input current (vin = dv dd ) ? ? 40 a input current (vin = dv ss ) ? 40 ? ? a c-bus interface and logic inputs input logic 1 70% ? ? dv dd input logic 0 ? ? 30% dv dd input leakage current (logic 1 or 0) 21 ? 1.0 ? 1.0 a input capacitance ? ? 7.5 pf c-bus interface and logic outputs output logic 1 (i oh = 120a) 90% ? ? dv dd (i oh = 1ma) 80% ? ? dv dd output logic 0 (i ol = 360a) ? ? 10% dv dd (i ol = -1.5ma) ? ? 15% dv dd ?off? state leakage current 21 ? ? 10 a irqn (vout = dv dd ) ? 1.0 ? +1.0 a rdata (output hiz) ? 1.0 ? +1.0 a v bias 26 output voltage offset wrt av dd /2 (i ol < 1 a) ? 2% ? av dd output impedance ? 22 ? k notes: 25 characteristics when driving the xtal/clk pin with an external clock source. 26 applies when utilising v bias to provide a reference voltage to other parts of the system. when using v bias as a reference, v bias must be buffered. v bias must always be decoupled with a capacitor as shown in figure 2.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 67 d/148/6 ac parameters notes min. typ. max. unit xtal/clk input ?high? pulse width 31 15 ? ? ns ?low? pulse width 31 15 ? ? ns input impedance (measured at 6.144mhz) powered-up resistance ? 150 ? k capacitance ? 20 ? pf powered-down resistance ? 300 ? k capacitance ? 20 ? pf xtal start-up time (from powersave) ? 400 ? ms v bias start-up time (from powersave) ? 30 ? ms microphone, signal and discriminator inputs (mic, sig, disc) input impedance 34 ? 1 ? m maximum input level (p-p) 35 ? ? 80% av dd load resistance (feedback pins) 80 ? ? k amplifier open loop voltage gain ? (i/p = 1mv rms at 100hz) ? ? 60 ? db unity gain bandwidth ? 1.0 ? mhz programmable input gain stage 36 gain (at 0db) 37 ? 0.5 0 +0.5 db cumulative gain error ? (wrt gain at 0db) ? 37 ? 1.0 0 +1.0 db notes: 31 timing for an external input to the xtal/clk pin. 34 with no external components connected. 35 centred about av dd /2; after multiplying by the gain of input circuit (with external components connected). 36 gain applied to signal at output of bu ffer amplifier: discfb, sigfb or micfb 37 design value for this block only in test mode. overall gain input to output has a tolerance of 0db 1.0db.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 68 d/148/6 ac parameters notes min. typ. max. unit modulator outputs 1/2 and audio output (mod1, mod2, audio) power-up to output stable 41 ? 50 100 s modulator attenuators attenuation (at 0db) 43 ? 1.0 0 +1.0 db cumulative attenuation error ? (wrt attenuation at 0db) ? ? 0.6 0 +0.6 db output impedance ? enabled 42 ? 600 ? ? disabled 42 ? 500 ? k output current range (av dd = 3.3v) ? ? 125 a output voltage range 44 0.5 ? av dd ?0.5 v load resistance 20 ? ? k audio attenuator attenuation (at 0db) 43 ? 1.0 0 +1.0 db cumulative attenuation error ? (wrt attenuation at 0db) ? ? 1.0 0 +1.0 db output impedance ? enabled 42 ? 600 ? ? disabled 42 ? 500 ? k output current range (av dd = 3.3v) ? ? 125 a output voltage range 44 0.5 ? av dd ?0.5 v load resistance 20 ? ? k notes: 41 power-up refers to issuing a c-bus command to turn on an output. these limits apply only if v bias is on and stable. at power s upply switch-on, the default state is for all blocks, except the xtal and c-bus interface, to be placed in powersave mode. 42 small signal impedance, at av dd = 3.3v and tamb = 25c. 43 with respect to the signal at t he feedback pin of the selected input port. 44 centred about av dd /2; with respect to the output driving a 20k load to av dd /2.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 69 d/148/6 ac parameters (cont.) notes min. typ. max. unit auxiliary signal inputs (auxadc1-4) source output impedance 51 ? ? 24 k auxiliary 10-bit adcs resolution ? 10 ? bits maximum input level (p-p) 54 ? ? 80% av dd conversion time 52 ? 250 ? s input impedance resistance ? 10 ? m capacitance ? 5 ? pf zero error ? (input offset to give adc output = 0) ? 0 ? 10 mv integral non-linearity ? ? 3 lsbs differential non-linearity 53 ? ? 1 lsbs auxiliary 10-bit dacs resolution ? 10 ? bits maximum output level (p-p), no load 54 80% ? ? av dd zero error ? (output offset from a dac input = 0) ? 0 ? 10 mv resistive load 5 ? ? k integral non-linearity ? ? 4 lsbs differential non-linearity 53 ? ? 1 lsbs notes: 51 denotes output impedance of the driver of the auxiliary input signal, to ensure < 1 bit additional error under nominal conditions. 52 with an auxiliary clock frequency of 3.6864mhz. 53 guaranteed monotonic with no missing codes. 54 level centred about av dd /2.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 70 d/148/6 9.1.4. parametric performance for the following conditions unless otherwise specified: external components as recommended in figure 2. maximum load on digital outputs = 30pf. xtal frequency = 6.144mhz 0.01% (100ppm) ); tamb = ? 40c to +85c. av dd = dv dd = 3.0v to 3.6v. reference signal level = 308mvrms at 1khz with av dd = 3.3v. signal levels track with supply voltage, so scale accordingly. signal to noise ratio (snr) in bit rate bandwidth. input stage gain = 0db, ou tput stage gain = 0db. ac parameters (cont.) notes min. typ. max. unit receiver signal type identification probability of correctly identifying signal type (snr = 12db) ? >>99.9 ? % msk/ffsk decoder signal input dynamic range 74 100 ? 800 mvrms bit error rate (snr = 20db) 74 ? <1 ? 10 -8 receiver synchronisation (snr = 12db) probability of bit 16 being correct ? >99.9 ? % notes: 74 av dd = 3.3v, for a ?101010101 ? 01? pattern measured at the input amplifier feedback pin. signal level scales with av dd .
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 71 d/148/6 ac parameters (cont.) notes min. typ. max. unit dtmf decoder sensitivity ? ? 22 +3 db response time ? 35 ? ms de-response time ? ? 45 ms falsing rate (per 30min voice input) ? 10 ? frequency tolerance ? 2.5 ? % twist ? 10 ? +10 db audio compandor attack time ? 4.0 ? ms decay time ? 13 ? ms 0db point 84 ? 100 ? mvrms compression/expansion ratio ? 2:1 ? dtmf encoder output signal level 84,85 ? 775 ? mvrms output level variation db output distortion ? ? 5 % msk/ffsk encoder output signal level 84 ? 775 ? mvrms output level variation ? 1.0 0 +1.0 db output distortion ? ? 5 % 3 rd harmonic distortion ? ? 3 % logic 1 frequency 1200baud and 2400baud 1198 1200 1202 hz logic 0 frequency 1200baud 1798 1800 1802 hz 2400baud 2398 2400 2402 hz isochronous distortion (0 to 1 and 1 to 0) ? ? 40 s notes: 84 av dd = 3.3v. 85 measured in single tone mode, p1.0 set to $daa0.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 72 d/148/6 ac parameters (cont.) notes min. typ. max. unit analogue channel audio filtering pass-band (nominal bandwidth): received audio 91 300 ? 3300 hz 12.5khz channel transmitted audio 92 300 ? 2550 hz 25khz channel transmitted audio 93 300 ? 3000 hz pass-band gain (at 1.0khz) ? 0 ? db pass-band ripple (wrt gain at 1.0khz) ? 2.0 0 +0.5 db stop-band attenuation 33.0 ? ? db residual hum and noise tx 96 ? ? 47 ? dbm residual hum and noise rx 96 ? ? 74 ? dbm pre-emphasis 94 ? +6 ? db/oct de-emphasis 95 ? ? 6 ? db/oct audio scrambler inversion frequency 98 2632 3300 3496 hz pass-band 99 300 ? 3000 hz audio expandor input signal range 97 ? ? 0.55 vrms notes: 91 the receiver audio filter complies with the characteristic shown in figure 7. the high pass filtering removes sub-audio components from the audio signal. 92 the 12.5khz channel filter complies with the characteristic shown in figure 11. 93 the 25khz channel filter complies with the characteristic shown in figure 10. 94 the pre-emphasis filter complies with the characteristic shown in figure 12. 95 the de-emphasis filter complies wi th the characteristic shown in figure 12. 96 psophometrically weighted. pre/de -emphasis, compandor and 25khz channel filter selected. 97 98 99 av dd = 3.3v. use of a scrambler inversion frequency other than 3300hz will shift the scrambled voice signal outside the audio band, so that some of the signal will be lost in the channel filter. the result is that the de scrambled voice signal will have a restricted bandwidth. the limits quoted are subjective and relate to the onset of a loss of speech intelligibility. -6db points, assuming default inversion frequency in use.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 73 d/148/6 9.2. c-bus timing figure 25 c-bus timing c-bus timing notes min. typ. max. unit t cse csn enable to sclk high time 100 ? ? ns t csh last sclk high to csn high time 100 ? ? ns t loz sclk low to rdata output enable time 0.0 ? ? ns t hiz csn high to rdata high impedance ? ? 1.0 s t csoff csn high time between transactions 1.0 ? ? s t nxt inter-byte time 200 ? ? ns t ck sclk cycle time 200 ? ? ns t ch sclk high time 100 ? ? ns t cl sclk low time 100 ? ? ns t cds cdata setup time 75 ? ? ns t cdh cdata hold time 25 ? ? ns t rds rdata setup time 50 ? ? ns t rdh rdata hold time 0 ? ? ns notes: 1. depending on the command, 1 or 2 bytes of cdata are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) las t. rdata is read from the peripher al msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the peripheral on the rising sclk edge. 3. commands are acted upon at the end of each command (rising edge of csn). 4. to allow for differing c serial interface formats c-bus compatible ics are able to work with sclk pulses starting and ending at either polarity. 5. maximum 30pf load on irqn pin and each c-bus interface line.
pmr audio and data processor CMX148 ? 2010 cml microsystems plc 74 d/148/6 these timings are for the latest version of c-bus and allow faster transfers than the original c-bus timing specification. the CMX148 can be used in conj unction with devices that comply with the slower timings, subject to system throughput constraints. 9.3. packaging figure 26 mechanical outline of 48-pin vqfn (q3) order as part no. CMX148q3
twr audio processor CMX148 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circu it patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of test ing every product shipped using calibrated test equipment to ensure compliance with thi s product specification. specific testing of all circuit parameters is not necessarily performed. figure 27 mechanical outline of 48-pin lqfp (l4) order as part no. CMX148l4 as package dimensions may change after publication of this datasheet, it is recommended that you check for the latest packaging information from the data sheet page of the cml webs ite: [www.cmlmicro.com].

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